175406Sache/* 275406Sache * Copyright 2019 Advanced Micro Devices, Inc. 375406Sache * 475406Sache * Permission is hereby granted, free of charge, to any person obtaining a 575406Sache * copy of this software and associated documentation files (the "Software"), 675406Sache * to deal in the Software without restriction, including without limitation 775406Sache * the rights to use, copy, modify, merge, publish, distribute, sublicense, 875406Sache * and/or sell copies of the Software, and to permit persons to whom the 975406Sache * Software is furnished to do so, subject to the following conditions: 1075406Sache * 1175406Sache * The above copyright notice and this permission notice shall be included in 1275406Sache * all copies or substantial portions of the Software. 1375406Sache * 1475406Sache * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1575406Sache * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1675406Sache * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1775406Sache * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1875406Sache * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1975406Sache * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2075406Sache * OTHER DEALINGS IN THE SOFTWARE. 2175406Sache * 2275406Sache */ 2375406Sache 2475406Sache#include "amdgpu.h" 2575406Sache#include "athub_v2_1.h" 2675406Sache 2775406Sache#include "athub/athub_2_1_0_offset.h" 2875406Sache#include "athub/athub_2_1_0_sh_mask.h" 2975406Sache 3075406Sache#include "soc15_common.h" 3175406Sache 3275406Sachestatic void 33119610Sacheathub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 34119610Sache bool enable) 35119610Sache{ 36119610Sache uint32_t def, data; 3775406Sache 38119610Sache def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 39119610Sache 40119610Sache if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 4175406Sache data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 42119610Sache else 43119610Sache data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 44119610Sache 4575406Sache if (def != data) 4675406Sache WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 4775406Sache} 4875406Sache 4975406Sachestatic void 5075406Sacheathub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 5175406Sache bool enable) 5275406Sache{ 5375406Sache uint32_t def, data; 5475406Sache 5575406Sache def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 5675406Sache 5775406Sache if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 5875406Sache (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 5975406Sache data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 6075406Sache else 6175406Sache data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 6275406Sache 6375406Sache if(def != data) 6475406Sache WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 6575406Sache} 6675406Sache 6775406Sacheint athub_v2_1_set_clockgating(struct amdgpu_device *adev, 6875406Sache enum amd_clockgating_state state) 6975406Sache{ 7075406Sache if (amdgpu_sriov_vf(adev)) 7175406Sache return 0; 7275406Sache 7375406Sache switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { 7475406Sache case IP_VERSION(2, 1, 0): 7575406Sache case IP_VERSION(2, 1, 1): 7675406Sache case IP_VERSION(2, 1, 2): 7775406Sache case IP_VERSION(2, 4, 0): 7875406Sache athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); 7975406Sache athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE); 8075406Sache break; 8175406Sache default: 8275406Sache break; 8375406Sache } 8475406Sache 8575406Sache return 0; 8675406Sache} 8775406Sache 8875406Sachevoid athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) 8975406Sache{ 9075406Sache int data; 9175406Sache 9275406Sache /* AMD_CG_SUPPORT_ATHUB_MGCG */ 9375406Sache data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 9475406Sache if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 9575406Sache *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; 9675406Sache 9775406Sache /* AMD_CG_SUPPORT_ATHUB_LS */ 9875406Sache if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) 9975406Sache *flags |= AMD_CG_SUPPORT_ATHUB_LS; 10075406Sache} 10175406Sache