1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_VCE_H__
25#define __AMDGPU_VCE_H__
26
27#define AMDGPU_MAX_VCE_HANDLES	16
28#define AMDGPU_VCE_FIRMWARE_OFFSET 256
29
30#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
31#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
32
33#define AMDGPU_VCE_FW_53_45	((53 << 24) | (45 << 16))
34
35struct amdgpu_vce {
36	struct amdgpu_bo	*vcpu_bo;
37	uint64_t		gpu_addr;
38	void			*cpu_addr;
39	void			*saved_bo;
40	unsigned		fw_version;
41	unsigned		fb_version;
42	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
43	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
44	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];
45	struct delayed_work	idle_work;
46	struct mutex		idle_mutex;
47	const struct firmware	*fw;	/* VCE firmware */
48	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
49	struct amdgpu_irq_src	irq;
50	unsigned		harvest_config;
51	struct drm_sched_entity	entity;
52	uint32_t                srbm_soft_reset;
53	unsigned		num_rings;
54};
55
56int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
57int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
58int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
59int amdgpu_vce_suspend(struct amdgpu_device *adev);
60int amdgpu_vce_resume(struct amdgpu_device *adev);
61void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
62int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
63			     struct amdgpu_ib *ib);
64int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
65				struct amdgpu_job *job,
66				struct amdgpu_ib *ib);
67void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
68				struct amdgpu_ib *ib, uint32_t flags);
69void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
70				unsigned flags);
71int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
72int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
73void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
74void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
75unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
76unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
77enum amdgpu_ring_priority_level amdgpu_vce_get_ring_prio(int ring);
78
79#endif
80