1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * exynos_ppmu.h - Exynos PPMU header file
4 *
5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
6 * Author : Chanwoo Choi <cw00.choi@samsung.com>
7 */
8
9#ifndef __EXYNOS_PPMU_H__
10#define __EXYNOS_PPMU_H__
11
12enum ppmu_state {
13	PPMU_DISABLE = 0,
14	PPMU_ENABLE,
15};
16
17enum ppmu_counter {
18	PPMU_PMNCNT0 = 0,
19	PPMU_PMNCNT1,
20	PPMU_PMNCNT2,
21	PPMU_PMNCNT3,
22
23	PPMU_PMNCNT_MAX,
24};
25
26/***
27 * PPMUv1.1 Definitions
28 */
29enum ppmu_event_type {
30	PPMU_RO_BUSY_CYCLE_CNT	= 0x0,
31	PPMU_WO_BUSY_CYCLE_CNT	= 0x1,
32	PPMU_RW_BUSY_CYCLE_CNT	= 0x2,
33	PPMU_RO_REQUEST_CNT	= 0x3,
34	PPMU_WO_REQUEST_CNT	= 0x4,
35	PPMU_RO_DATA_CNT	= 0x5,
36	PPMU_WO_DATA_CNT	= 0x6,
37	PPMU_RO_LATENCY		= 0x12,
38	PPMU_WO_LATENCY		= 0x16,
39};
40
41enum ppmu_reg {
42	/* PPC control register */
43	PPMU_PMNC		= 0x00,
44	PPMU_CNTENS		= 0x10,
45	PPMU_CNTENC		= 0x20,
46	PPMU_INTENS		= 0x30,
47	PPMU_INTENC		= 0x40,
48	PPMU_FLAG		= 0x50,
49
50	/* Cycle Counter and Performance Event Counter Register */
51	PPMU_CCNT		= 0x100,
52	PPMU_PMCNT0		= 0x110,
53	PPMU_PMCNT1		= 0x120,
54	PPMU_PMCNT2		= 0x130,
55	PPMU_PMCNT3_HIGH	= 0x140,
56	PPMU_PMCNT3_LOW		= 0x150,
57
58	/* Bus Event Generator */
59	PPMU_BEVT0SEL		= 0x1000,
60	PPMU_BEVT1SEL		= 0x1100,
61	PPMU_BEVT2SEL		= 0x1200,
62	PPMU_BEVT3SEL		= 0x1300,
63	PPMU_COUNTER_RESET	= 0x1810,
64	PPMU_READ_OVERFLOW_CNT	= 0x1810,
65	PPMU_READ_UNDERFLOW_CNT	= 0x1814,
66	PPMU_WRITE_OVERFLOW_CNT	= 0x1850,
67	PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
68	PPMU_READ_PENDING_CNT	= 0x1880,
69	PPMU_WRITE_PENDING_CNT	= 0x1884
70};
71
72/* PMNC register */
73#define PPMU_PMNC_CC_RESET_SHIFT	2
74#define PPMU_PMNC_COUNTER_RESET_SHIFT	1
75#define PPMU_PMNC_ENABLE_SHIFT		0
76#define PPMU_PMNC_START_MODE_MASK	BIT(16)
77#define PPMU_PMNC_CC_DIVIDER_MASK	BIT(3)
78#define PPMU_PMNC_CC_RESET_MASK		BIT(2)
79#define PPMU_PMNC_COUNTER_RESET_MASK	BIT(1)
80#define PPMU_PMNC_ENABLE_MASK		BIT(0)
81
82/* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
83#define PPMU_CCNT_MASK			BIT(31)
84#define PPMU_PMCNT3_MASK		BIT(3)
85#define PPMU_PMCNT2_MASK		BIT(2)
86#define PPMU_PMCNT1_MASK		BIT(1)
87#define PPMU_PMCNT0_MASK		BIT(0)
88
89/* PPMU_PMNCTx/PPMU_BETxSEL registers */
90#define PPMU_PMNCT(x)			(PPMU_PMCNT0 + (0x10 * x))
91#define PPMU_BEVTxSEL(x)		(PPMU_BEVT0SEL + (0x100 * x))
92
93/***
94 * PPMU_V2.0 definitions
95 */
96enum ppmu_v2_mode {
97	PPMU_V2_MODE_MANUAL = 0,
98	PPMU_V2_MODE_AUTO = 1,
99	PPMU_V2_MODE_CIG = 2,	/* CIG (Conditional Interrupt Generation) */
100};
101
102enum ppmu_v2_event_type {
103	PPMU_V2_RO_DATA_CNT	= 0x4,
104	PPMU_V2_WO_DATA_CNT	= 0x5,
105
106	PPMU_V2_EVT3_RW_DATA_CNT = 0x22,	/* Only for Event3 */
107};
108
109enum ppmu_V2_reg {
110	/* PPC control register */
111	PPMU_V2_PMNC		= 0x04,
112	PPMU_V2_CNTENS		= 0x08,
113	PPMU_V2_CNTENC		= 0x0c,
114	PPMU_V2_INTENS		= 0x10,
115	PPMU_V2_INTENC		= 0x14,
116	PPMU_V2_FLAG		= 0x18,
117
118	/* Cycle Counter and Performance Event Counter Register */
119	PPMU_V2_CCNT		= 0x48,
120	PPMU_V2_PMCNT0		= 0x34,
121	PPMU_V2_PMCNT1		= 0x38,
122	PPMU_V2_PMCNT2		= 0x3c,
123	PPMU_V2_PMCNT3_LOW	= 0x40,
124	PPMU_V2_PMCNT3_HIGH	= 0x44,
125
126	/* Bus Event Generator */
127	PPMU_V2_CIG_CFG0		= 0x1c,
128	PPMU_V2_CIG_CFG1		= 0x20,
129	PPMU_V2_CIG_CFG2		= 0x24,
130	PPMU_V2_CIG_RESULT	= 0x28,
131	PPMU_V2_CNT_RESET	= 0x2c,
132	PPMU_V2_CNT_AUTO		= 0x30,
133	PPMU_V2_CH_EV0_TYPE	= 0x200,
134	PPMU_V2_CH_EV1_TYPE	= 0x204,
135	PPMU_V2_CH_EV2_TYPE	= 0x208,
136	PPMU_V2_CH_EV3_TYPE	= 0x20c,
137	PPMU_V2_SM_ID_V		= 0x220,
138	PPMU_V2_SM_ID_A		= 0x224,
139	PPMU_V2_SM_OTHERS_V	= 0x228,
140	PPMU_V2_SM_OTHERS_A	= 0x22c,
141	PPMU_V2_INTERRUPT_RESET	= 0x260,
142};
143
144/* PMNC register */
145#define PPMU_V2_PMNC_START_MODE_SHIFT	20
146#define PPMU_V2_PMNC_START_MODE_MASK	(0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
147
148#define PPMU_PMNC_CC_RESET_SHIFT	2
149#define PPMU_PMNC_COUNTER_RESET_SHIFT	1
150#define PPMU_PMNC_ENABLE_SHIFT		0
151#define PPMU_PMNC_START_MODE_MASK	BIT(16)
152#define PPMU_PMNC_CC_DIVIDER_MASK	BIT(3)
153#define PPMU_PMNC_CC_RESET_MASK		BIT(2)
154#define PPMU_PMNC_COUNTER_RESET_MASK	BIT(1)
155#define PPMU_PMNC_ENABLE_MASK		BIT(0)
156
157#define PPMU_V2_PMNCT(x)		(PPMU_V2_PMCNT0 + (0x4 * x))
158#define PPMU_V2_CH_EVx_TYPE(x)		(PPMU_V2_CH_EV0_TYPE + (0x4 * x))
159
160#endif /* __EXYNOS_PPMU_H__ */
161