1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2022 Intel Corporation */
3#include "adf_accel_devices.h"
4#include "icp_qat_fw_comp.h"
5#include "icp_qat_hw_20_comp.h"
6#include "adf_gen4_dc.h"
7
8static void qat_comp_build_deflate(void *ctx)
9{
10	struct icp_qat_fw_comp_req *req_tmpl =
11				(struct icp_qat_fw_comp_req *)ctx;
12	struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
13	struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
14	struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
15	struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = {0};
16	struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = {0};
17	struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = {0};
18	u32 upper_val;
19	u32 lower_val;
20
21	memset(req_tmpl, 0, sizeof(*req_tmpl));
22	header->hdr_flags =
23		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
24	header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
25	header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
26	header->comn_req_flags =
27		ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
28					    QAT_COMN_PTR_TYPE_SGL);
29	header->serv_specif_flags =
30		ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
31					    ICP_QAT_FW_COMP_AUTO_SELECT_BEST,
32					    ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
33					    ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
34					    ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
35	hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
36	hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
37	hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
38	hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
39	hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
40	hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
41	hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
42	hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
43
44	upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
45	lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
46
47	cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
48	cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
49
50	req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
51	req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
52	req_pars->req_par_flags =
53		ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
54						      ICP_QAT_FW_COMP_EOP,
55						      ICP_QAT_FW_COMP_BFINAL,
56						      ICP_QAT_FW_COMP_CNV,
57						      ICP_QAT_FW_COMP_CNV_RECOVERY,
58						      ICP_QAT_FW_COMP_NO_CNV_DFX,
59						      ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
60						      ICP_QAT_FW_COMP_NO_XXHASH_ACC,
61						      ICP_QAT_FW_COMP_CNV_ERROR_NONE,
62						      ICP_QAT_FW_COMP_NO_APPEND_CRC,
63						      ICP_QAT_FW_COMP_NO_DROP_DATA);
64
65	/* Fill second half of the template for decompression */
66	memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
67	req_tmpl++;
68	header = &req_tmpl->comn_hdr;
69	header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
70	cd_pars = &req_tmpl->cd_pars;
71
72	hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
73	lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
74
75	cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
76	cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
77}
78
79void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
80{
81	dc_ops->build_deflate_ctx = qat_comp_build_deflate;
82}
83EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);
84