1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2022 HiSilicon Limited. */ 3#ifndef QM_COMMON_H 4#define QM_COMMON_H 5 6#define QM_DBG_READ_LEN 256 7 8struct qm_cqe { 9 __le32 rsvd0; 10 __le16 cmd_id; 11 __le16 rsvd1; 12 __le16 sq_head; 13 __le16 sq_num; 14 __le16 rsvd2; 15 __le16 w7; 16}; 17 18struct qm_eqe { 19 __le32 dw0; 20}; 21 22struct qm_aeqe { 23 __le32 dw0; 24}; 25 26struct qm_sqc { 27 __le16 head; 28 __le16 tail; 29 __le32 base_l; 30 __le32 base_h; 31 __le32 dw3; 32 __le16 w8; 33 __le16 rsvd0; 34 __le16 pasid; 35 __le16 w11; 36 __le16 cq_num; 37 __le16 w13; 38 __le32 rsvd1; 39}; 40 41struct qm_cqc { 42 __le16 head; 43 __le16 tail; 44 __le32 base_l; 45 __le32 base_h; 46 __le32 dw3; 47 __le16 w8; 48 __le16 rsvd0; 49 __le16 pasid; 50 __le16 w11; 51 __le32 dw6; 52 __le32 rsvd1; 53}; 54 55struct qm_eqc { 56 __le16 head; 57 __le16 tail; 58 __le32 base_l; 59 __le32 base_h; 60 __le32 dw3; 61 __le32 rsvd[2]; 62 __le32 dw6; 63}; 64 65struct qm_aeqc { 66 __le16 head; 67 __le16 tail; 68 __le32 base_l; 69 __le32 base_h; 70 __le32 dw3; 71 __le32 rsvd[2]; 72 __le32 dw6; 73}; 74 75int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op); 76void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm); 77void hisi_qm_set_algqos_init(struct hisi_qm *qm); 78 79#endif 80