1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
4 * M (part of the Centrino chipset).
5 *
6 * Since the original Pentium M, most new Intel CPUs support Enhanced
7 * SpeedStep.
8 *
9 * Despite the "SpeedStep" in the name, this is almost entirely unlike
10 * traditional SpeedStep.
11 *
12 * Modelled on speedstep.c
13 *
14 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/cpufreq.h>
23#include <linux/sched.h>	/* current */
24#include <linux/delay.h>
25#include <linux/compiler.h>
26#include <linux/gfp.h>
27
28#include <asm/msr.h>
29#include <asm/processor.h>
30#include <asm/cpufeature.h>
31#include <asm/cpu_device_id.h>
32
33#define MAINTAINER	"linux-pm@vger.kernel.org"
34
35#define INTEL_MSR_RANGE	(0xffff)
36
37struct cpu_id
38{
39	__u8	x86;            /* CPU family */
40	__u8	x86_model;	/* model */
41	__u8	x86_stepping;	/* stepping */
42};
43
44enum {
45	CPU_BANIAS,
46	CPU_DOTHAN_A1,
47	CPU_DOTHAN_A2,
48	CPU_DOTHAN_B0,
49	CPU_MP4HT_D0,
50	CPU_MP4HT_E0,
51};
52
53static const struct cpu_id cpu_ids[] = {
54	[CPU_BANIAS]	= { 6,  9, 5 },
55	[CPU_DOTHAN_A1]	= { 6, 13, 1 },
56	[CPU_DOTHAN_A2]	= { 6, 13, 2 },
57	[CPU_DOTHAN_B0]	= { 6, 13, 6 },
58	[CPU_MP4HT_D0]	= {15,  3, 4 },
59	[CPU_MP4HT_E0]	= {15,  4, 1 },
60};
61#define N_IDS	ARRAY_SIZE(cpu_ids)
62
63struct cpu_model
64{
65	const struct cpu_id *cpu_id;
66	const char	*model_name;
67	unsigned	max_freq; /* max clock in kHz */
68
69	struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
70};
71static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
72				  const struct cpu_id *x);
73
74/* Operating points for current CPU */
75static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
76static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
77
78static struct cpufreq_driver centrino_driver;
79
80#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
81
82/* Computes the correct form for IA32_PERF_CTL MSR for a particular
83   frequency/voltage operating point; frequency in MHz, volts in mV.
84   This is stored as "driver_data" in the structure. */
85#define OP(mhz, mv)							\
86	{								\
87		.frequency = (mhz) * 1000,				\
88		.driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16)		\
89	}
90
91/*
92 * These voltage tables were derived from the Intel Pentium M
93 * datasheet, document 25261202.pdf, Table 5.  I have verified they
94 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
95 * M.
96 */
97
98/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
99static struct cpufreq_frequency_table banias_900[] =
100{
101	OP(600,  844),
102	OP(800,  988),
103	OP(900, 1004),
104	{ .frequency = CPUFREQ_TABLE_END }
105};
106
107/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
108static struct cpufreq_frequency_table banias_1000[] =
109{
110	OP(600,   844),
111	OP(800,   972),
112	OP(900,   988),
113	OP(1000, 1004),
114	{ .frequency = CPUFREQ_TABLE_END }
115};
116
117/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
118static struct cpufreq_frequency_table banias_1100[] =
119{
120	OP( 600,  956),
121	OP( 800, 1020),
122	OP( 900, 1100),
123	OP(1000, 1164),
124	OP(1100, 1180),
125	{ .frequency = CPUFREQ_TABLE_END }
126};
127
128
129/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
130static struct cpufreq_frequency_table banias_1200[] =
131{
132	OP( 600,  956),
133	OP( 800, 1004),
134	OP( 900, 1020),
135	OP(1000, 1100),
136	OP(1100, 1164),
137	OP(1200, 1180),
138	{ .frequency = CPUFREQ_TABLE_END }
139};
140
141/* Intel Pentium M processor 1.30GHz (Banias) */
142static struct cpufreq_frequency_table banias_1300[] =
143{
144	OP( 600,  956),
145	OP( 800, 1260),
146	OP(1000, 1292),
147	OP(1200, 1356),
148	OP(1300, 1388),
149	{ .frequency = CPUFREQ_TABLE_END }
150};
151
152/* Intel Pentium M processor 1.40GHz (Banias) */
153static struct cpufreq_frequency_table banias_1400[] =
154{
155	OP( 600,  956),
156	OP( 800, 1180),
157	OP(1000, 1308),
158	OP(1200, 1436),
159	OP(1400, 1484),
160	{ .frequency = CPUFREQ_TABLE_END }
161};
162
163/* Intel Pentium M processor 1.50GHz (Banias) */
164static struct cpufreq_frequency_table banias_1500[] =
165{
166	OP( 600,  956),
167	OP( 800, 1116),
168	OP(1000, 1228),
169	OP(1200, 1356),
170	OP(1400, 1452),
171	OP(1500, 1484),
172	{ .frequency = CPUFREQ_TABLE_END }
173};
174
175/* Intel Pentium M processor 1.60GHz (Banias) */
176static struct cpufreq_frequency_table banias_1600[] =
177{
178	OP( 600,  956),
179	OP( 800, 1036),
180	OP(1000, 1164),
181	OP(1200, 1276),
182	OP(1400, 1420),
183	OP(1600, 1484),
184	{ .frequency = CPUFREQ_TABLE_END }
185};
186
187/* Intel Pentium M processor 1.70GHz (Banias) */
188static struct cpufreq_frequency_table banias_1700[] =
189{
190	OP( 600,  956),
191	OP( 800, 1004),
192	OP(1000, 1116),
193	OP(1200, 1228),
194	OP(1400, 1308),
195	OP(1700, 1484),
196	{ .frequency = CPUFREQ_TABLE_END }
197};
198#undef OP
199
200#define _BANIAS(cpuid, max, name)	\
201{	.cpu_id		= cpuid,	\
202	.model_name	= "Intel(R) Pentium(R) M processor " name "MHz", \
203	.max_freq	= (max)*1000,	\
204	.op_points	= banias_##max,	\
205}
206#define BANIAS(max)	_BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
207
208/* CPU models, their operating frequency range, and freq/voltage
209   operating points */
210static struct cpu_model models[] =
211{
212	_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
213	BANIAS(1000),
214	BANIAS(1100),
215	BANIAS(1200),
216	BANIAS(1300),
217	BANIAS(1400),
218	BANIAS(1500),
219	BANIAS(1600),
220	BANIAS(1700),
221
222	/* NULL model_name is a wildcard */
223	{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
224	{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
225	{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
226	{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
227	{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
228
229	{ NULL, }
230};
231#undef _BANIAS
232#undef BANIAS
233
234static int centrino_cpu_init_table(struct cpufreq_policy *policy)
235{
236	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
237	struct cpu_model *model;
238
239	for(model = models; model->cpu_id != NULL; model++)
240		if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
241		    (model->model_name == NULL ||
242		     strcmp(cpu->x86_model_id, model->model_name) == 0))
243			break;
244
245	if (model->cpu_id == NULL) {
246		/* No match at all */
247		pr_debug("no support for CPU model \"%s\": "
248		       "send /proc/cpuinfo to " MAINTAINER "\n",
249		       cpu->x86_model_id);
250		return -ENOENT;
251	}
252
253	if (model->op_points == NULL) {
254		/* Matched a non-match */
255		pr_debug("no table support for CPU model \"%s\"\n",
256		       cpu->x86_model_id);
257		pr_debug("try using the acpi-cpufreq driver\n");
258		return -ENOENT;
259	}
260
261	per_cpu(centrino_model, policy->cpu) = model;
262
263	pr_debug("found \"%s\": max frequency: %dkHz\n",
264	       model->model_name, model->max_freq);
265
266	return 0;
267}
268
269#else
270static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
271{
272	return -ENODEV;
273}
274#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
275
276static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
277				  const struct cpu_id *x)
278{
279	if ((c->x86 == x->x86) &&
280	    (c->x86_model == x->x86_model) &&
281	    (c->x86_stepping == x->x86_stepping))
282		return 1;
283	return 0;
284}
285
286/* To be called only after centrino_model is initialized */
287static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
288{
289	int i;
290
291	/*
292	 * Extract clock in kHz from PERF_CTL value
293	 * for centrino, as some DSDTs are buggy.
294	 * Ideally, this can be done using the acpi_data structure.
295	 */
296	if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
297	    (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
298	    (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
299		msr = (msr >> 8) & 0xff;
300		return msr * 100000;
301	}
302
303	if ((!per_cpu(centrino_model, cpu)) ||
304	    (!per_cpu(centrino_model, cpu)->op_points))
305		return 0;
306
307	msr &= 0xffff;
308	for (i = 0;
309		per_cpu(centrino_model, cpu)->op_points[i].frequency
310							!= CPUFREQ_TABLE_END;
311	     i++) {
312		if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
313			return per_cpu(centrino_model, cpu)->
314							op_points[i].frequency;
315	}
316	if (failsafe)
317		return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
318	else
319		return 0;
320}
321
322/* Return the current CPU frequency in kHz */
323static unsigned int get_cur_freq(unsigned int cpu)
324{
325	unsigned l, h;
326	unsigned clock_freq;
327
328	rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
329	clock_freq = extract_clock(l, cpu, 0);
330
331	if (unlikely(clock_freq == 0)) {
332		/*
333		 * On some CPUs, we can see transient MSR values (which are
334		 * not present in _PSS), while CPU is doing some automatic
335		 * P-state transition (like TM2). Get the last freq set
336		 * in PERF_CTL.
337		 */
338		rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
339		clock_freq = extract_clock(l, cpu, 1);
340	}
341	return clock_freq;
342}
343
344
345static int centrino_cpu_init(struct cpufreq_policy *policy)
346{
347	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
348	unsigned l, h;
349	int i;
350
351	/* Only Intel makes Enhanced Speedstep-capable CPUs */
352	if (cpu->x86_vendor != X86_VENDOR_INTEL ||
353	    !cpu_has(cpu, X86_FEATURE_EST))
354		return -ENODEV;
355
356	if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
357		centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
358
359	if (policy->cpu != 0)
360		return -ENODEV;
361
362	for (i = 0; i < N_IDS; i++)
363		if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
364			break;
365
366	if (i != N_IDS)
367		per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
368
369	if (!per_cpu(centrino_cpu, policy->cpu)) {
370		pr_debug("found unsupported CPU with "
371		"Enhanced SpeedStep: send /proc/cpuinfo to "
372		MAINTAINER "\n");
373		return -ENODEV;
374	}
375
376	if (centrino_cpu_init_table(policy))
377		return -ENODEV;
378
379	/* Check to see if Enhanced SpeedStep is enabled, and try to
380	   enable it if not. */
381	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
382
383	if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
384		l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
385		pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
386		wrmsr(MSR_IA32_MISC_ENABLE, l, h);
387
388		/* check to see if it stuck */
389		rdmsr(MSR_IA32_MISC_ENABLE, l, h);
390		if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
391			pr_info("couldn't enable Enhanced SpeedStep\n");
392			return -ENODEV;
393		}
394	}
395
396	policy->cpuinfo.transition_latency = 10000;
397						/* 10uS transition latency */
398	policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
399
400	return 0;
401}
402
403static int centrino_cpu_exit(struct cpufreq_policy *policy)
404{
405	unsigned int cpu = policy->cpu;
406
407	if (!per_cpu(centrino_model, cpu))
408		return -ENODEV;
409
410	per_cpu(centrino_model, cpu) = NULL;
411
412	return 0;
413}
414
415/**
416 * centrino_target - set a new CPUFreq policy
417 * @policy: new policy
418 * @index: index of target frequency
419 *
420 * Sets a new CPUFreq policy.
421 */
422static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
423{
424	unsigned int	msr, oldmsr = 0, h = 0, cpu = policy->cpu;
425	int			retval = 0;
426	unsigned int		j, first_cpu;
427	struct cpufreq_frequency_table *op_points;
428	cpumask_var_t covered_cpus;
429
430	if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
431		return -ENOMEM;
432
433	if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
434		retval = -ENODEV;
435		goto out;
436	}
437
438	first_cpu = 1;
439	op_points = &per_cpu(centrino_model, cpu)->op_points[index];
440	for_each_cpu(j, policy->cpus) {
441		int good_cpu;
442
443		/*
444		 * Support for SMP systems.
445		 * Make sure we are running on CPU that wants to change freq
446		 */
447		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
448			good_cpu = cpumask_any_and(policy->cpus,
449						   cpu_online_mask);
450		else
451			good_cpu = j;
452
453		if (good_cpu >= nr_cpu_ids) {
454			pr_debug("couldn't limit to CPUs in this domain\n");
455			retval = -EAGAIN;
456			if (first_cpu) {
457				/* We haven't started the transition yet. */
458				goto out;
459			}
460			break;
461		}
462
463		msr = op_points->driver_data;
464
465		if (first_cpu) {
466			rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
467			if (msr == (oldmsr & 0xffff)) {
468				pr_debug("no change needed - msr was and needs "
469					"to be %x\n", oldmsr);
470				retval = 0;
471				goto out;
472			}
473
474			first_cpu = 0;
475			/* all but 16 LSB are reserved, treat them with care */
476			oldmsr &= ~0xffff;
477			msr &= 0xffff;
478			oldmsr |= msr;
479		}
480
481		wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
482		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
483			break;
484
485		cpumask_set_cpu(j, covered_cpus);
486	}
487
488	if (unlikely(retval)) {
489		/*
490		 * We have failed halfway through the frequency change.
491		 * We have sent callbacks to policy->cpus and
492		 * MSRs have already been written on coverd_cpus.
493		 * Best effort undo..
494		 */
495
496		for_each_cpu(j, covered_cpus)
497			wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
498	}
499	retval = 0;
500
501out:
502	free_cpumask_var(covered_cpus);
503	return retval;
504}
505
506static struct cpufreq_driver centrino_driver = {
507	.name		= "centrino", /* should be speedstep-centrino,
508					 but there's a 16 char limit */
509	.init		= centrino_cpu_init,
510	.exit		= centrino_cpu_exit,
511	.verify		= cpufreq_generic_frequency_table_verify,
512	.target_index	= centrino_target,
513	.get		= get_cur_freq,
514	.attr		= cpufreq_generic_attr,
515};
516
517/*
518 * This doesn't replace the detailed checks above because
519 * the generic CPU IDs don't have a way to match for steppings
520 * or ASCII model IDs.
521 */
522static const struct x86_cpu_id centrino_ids[] = {
523	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL,  6,  9, X86_FEATURE_EST, NULL),
524	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL,  6, 13, X86_FEATURE_EST, NULL),
525	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15,  3, X86_FEATURE_EST, NULL),
526	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15,  4, X86_FEATURE_EST, NULL),
527	{}
528};
529
530/**
531 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
532 *
533 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
534 * unsupported devices, -ENOENT if there's no voltage table for this
535 * particular CPU model, -EINVAL on problems during initiatization,
536 * and zero on success.
537 *
538 * This is quite picky.  Not only does the CPU have to advertise the
539 * "est" flag in the cpuid capability flags, we look for a specific
540 * CPU model and stepping, and we need to have the exact model name in
541 * our voltage tables.  That is, be paranoid about not releasing
542 * someone's valuable magic smoke.
543 */
544static int __init centrino_init(void)
545{
546	if (!x86_match_cpu(centrino_ids))
547		return -ENODEV;
548	return cpufreq_register_driver(&centrino_driver);
549}
550
551static void __exit centrino_exit(void)
552{
553	cpufreq_unregister_driver(&centrino_driver);
554}
555
556MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
557MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
558MODULE_LICENSE ("GPL");
559
560late_initcall(centrino_init);
561module_exit(centrino_exit);
562