1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ADDI_TCW_H 3#define _ADDI_TCW_H 4 5/* 6 * Following are the generic definitions for the ADDI-DATA timer/counter/ 7 * watchdog (TCW) registers and bits. Some of the registers are not used 8 * depending on the use of the TCW. 9 */ 10 11#define ADDI_TCW_VAL_REG 0x00 12 13#define ADDI_TCW_SYNC_REG 0x00 14#define ADDI_TCW_SYNC_CTR_TRIG BIT(8) 15#define ADDI_TCW_SYNC_CTR_DIS BIT(7) 16#define ADDI_TCW_SYNC_CTR_ENA BIT(6) 17#define ADDI_TCW_SYNC_TIMER_TRIG BIT(5) 18#define ADDI_TCW_SYNC_TIMER_DIS BIT(4) 19#define ADDI_TCW_SYNC_TIMER_ENA BIT(3) 20#define ADDI_TCW_SYNC_WDOG_TRIG BIT(2) 21#define ADDI_TCW_SYNC_WDOG_DIS BIT(1) 22#define ADDI_TCW_SYNC_WDOG_ENA BIT(0) 23 24#define ADDI_TCW_RELOAD_REG 0x04 25 26#define ADDI_TCW_TIMEBASE_REG 0x08 27 28#define ADDI_TCW_CTRL_REG 0x0c 29#define ADDI_TCW_CTRL_EXT_CLK_STATUS BIT(21) 30#define ADDI_TCW_CTRL_CASCADE BIT(20) 31#define ADDI_TCW_CTRL_CNTR_ENA BIT(19) 32#define ADDI_TCW_CTRL_CNT_UP BIT(18) 33#define ADDI_TCW_CTRL_EXT_CLK(x) (((x) & 3) << 16) 34#define ADDI_TCW_CTRL_EXT_CLK_MASK ADDI_TCW_CTRL_EXT_CLK(3) 35#define ADDI_TCW_CTRL_MODE(x) (((x) & 7) << 13) 36#define ADDI_TCW_CTRL_MODE_MASK ADDI_TCW_CTRL_MODE(7) 37#define ADDI_TCW_CTRL_OUT(x) (((x) & 3) << 11) 38#define ADDI_TCW_CTRL_OUT_MASK ADDI_TCW_CTRL_OUT(3) 39#define ADDI_TCW_CTRL_GATE BIT(10) 40#define ADDI_TCW_CTRL_TRIG BIT(9) 41#define ADDI_TCW_CTRL_EXT_GATE(x) (((x) & 3) << 7) 42#define ADDI_TCW_CTRL_EXT_GATE_MASK ADDI_TCW_CTRL_EXT_GATE(3) 43#define ADDI_TCW_CTRL_EXT_TRIG(x) (((x) & 3) << 5) 44#define ADDI_TCW_CTRL_EXT_TRIG_MASK ADDI_TCW_CTRL_EXT_TRIG(3) 45#define ADDI_TCW_CTRL_TIMER_ENA BIT(4) 46#define ADDI_TCW_CTRL_RESET_ENA BIT(3) 47#define ADDI_TCW_CTRL_WARN_ENA BIT(2) 48#define ADDI_TCW_CTRL_IRQ_ENA BIT(1) 49#define ADDI_TCW_CTRL_ENA BIT(0) 50 51#define ADDI_TCW_STATUS_REG 0x10 52#define ADDI_TCW_STATUS_SOFT_CLR BIT(3) 53#define ADDI_TCW_STATUS_HARDWARE_TRIG BIT(2) 54#define ADDI_TCW_STATUS_SOFT_TRIG BIT(1) 55#define ADDI_TCW_STATUS_OVERFLOW BIT(0) 56 57#define ADDI_TCW_IRQ_REG 0x14 58#define ADDI_TCW_IRQ BIT(0) 59 60#define ADDI_TCW_WARN_TIMEVAL_REG 0x18 61 62#define ADDI_TCW_WARN_TIMEBASE_REG 0x1c 63 64#endif 65