1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (c) 2018 MediaTek Inc. 4// Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6#include <linux/clk-provider.h> 7#include <linux/platform_device.h> 8 9#include "clk-mtk.h" 10#include "clk-gate.h" 11 12#include <dt-bindings/clock/mt8183-clk.h> 13 14static const struct mtk_gate_regs ipu_core1_cg_regs = { 15 .set_ofs = 0x4, 16 .clr_ofs = 0x8, 17 .sta_ofs = 0x0, 18}; 19 20#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \ 21 GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \ 22 &mtk_clk_gate_ops_setclr) 23 24static const struct mtk_gate ipu_core1_clks[] = { 25 GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0), 26 GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1), 27 GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2), 28}; 29 30static const struct mtk_clk_desc ipu_core1_desc = { 31 .clks = ipu_core1_clks, 32 .num_clks = ARRAY_SIZE(ipu_core1_clks), 33}; 34 35static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = { 36 { 37 .compatible = "mediatek,mt8183-ipu_core1", 38 .data = &ipu_core1_desc, 39 }, { 40 /* sentinel */ 41 } 42}; 43MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core1); 44 45static struct platform_driver clk_mt8183_ipu_core1_drv = { 46 .probe = mtk_clk_simple_probe, 47 .remove_new = mtk_clk_simple_remove, 48 .driver = { 49 .name = "clk-mt8183-ipu_core1", 50 .of_match_table = of_match_clk_mt8183_ipu_core1, 51 }, 52}; 53module_platform_driver(clk_mt8183_ipu_core1_drv); 54MODULE_LICENSE("GPL"); 55