1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019-2021 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/firmware/imx/rsrc.h>
8
9#include "clk-scu.h"
10
11/* Keep sorted in the ascending order */
12static const u32 imx8qxp_clk_scu_rsrc_table[] = {
13	IMX_SC_R_DC_0_VIDEO0,
14	IMX_SC_R_DC_0_VIDEO1,
15	IMX_SC_R_DC_0,
16	IMX_SC_R_DC_0_PLL_0,
17	IMX_SC_R_DC_0_PLL_1,
18	IMX_SC_R_SPI_0,
19	IMX_SC_R_SPI_1,
20	IMX_SC_R_SPI_2,
21	IMX_SC_R_SPI_3,
22	IMX_SC_R_UART_0,
23	IMX_SC_R_UART_1,
24	IMX_SC_R_UART_2,
25	IMX_SC_R_UART_3,
26	IMX_SC_R_I2C_0,
27	IMX_SC_R_I2C_1,
28	IMX_SC_R_I2C_2,
29	IMX_SC_R_I2C_3,
30	IMX_SC_R_ADC_0,
31	IMX_SC_R_FTM_0,
32	IMX_SC_R_FTM_1,
33	IMX_SC_R_CAN_0,
34	IMX_SC_R_GPU_0_PID0,
35	IMX_SC_R_LCD_0,
36	IMX_SC_R_LCD_0_PWM_0,
37	IMX_SC_R_PWM_0,
38	IMX_SC_R_PWM_1,
39	IMX_SC_R_PWM_2,
40	IMX_SC_R_PWM_3,
41	IMX_SC_R_PWM_4,
42	IMX_SC_R_PWM_5,
43	IMX_SC_R_PWM_6,
44	IMX_SC_R_PWM_7,
45	IMX_SC_R_GPT_0,
46	IMX_SC_R_GPT_1,
47	IMX_SC_R_GPT_2,
48	IMX_SC_R_GPT_3,
49	IMX_SC_R_GPT_4,
50	IMX_SC_R_FSPI_0,
51	IMX_SC_R_FSPI_1,
52	IMX_SC_R_SDHC_0,
53	IMX_SC_R_SDHC_1,
54	IMX_SC_R_SDHC_2,
55	IMX_SC_R_ENET_0,
56	IMX_SC_R_ENET_1,
57	IMX_SC_R_USB_2,
58	IMX_SC_R_NAND,
59	IMX_SC_R_LVDS_0,
60	IMX_SC_R_LVDS_1,
61	IMX_SC_R_M4_0_UART,
62	IMX_SC_R_M4_0_I2C,
63	IMX_SC_R_ELCDIF_PLL,
64	IMX_SC_R_AUDIO_PLL_0,
65	IMX_SC_R_PI_0,
66	IMX_SC_R_PI_0_PWM_0,
67	IMX_SC_R_PI_0_I2C_0,
68	IMX_SC_R_PI_0_PLL,
69	IMX_SC_R_MIPI_0,
70	IMX_SC_R_MIPI_0_PWM_0,
71	IMX_SC_R_MIPI_0_I2C_0,
72	IMX_SC_R_MIPI_0_I2C_1,
73	IMX_SC_R_MIPI_1,
74	IMX_SC_R_MIPI_1_PWM_0,
75	IMX_SC_R_MIPI_1_I2C_0,
76	IMX_SC_R_MIPI_1_I2C_1,
77	IMX_SC_R_CSI_0,
78	IMX_SC_R_CSI_0_PWM_0,
79	IMX_SC_R_CSI_0_I2C_0,
80	IMX_SC_R_AUDIO_PLL_1,
81	IMX_SC_R_AUDIO_CLK_0,
82	IMX_SC_R_AUDIO_CLK_1,
83	IMX_SC_R_A35,
84	IMX_SC_R_VPU_DEC_0,
85	IMX_SC_R_VPU_ENC_0,
86};
87
88const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
89	.rsrc = imx8qxp_clk_scu_rsrc_table,
90	.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
91};
92