1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9/* Control and Status Register(BTINTEL_PCIE_CSR) */ 10#define BTINTEL_PCIE_CSR_BASE (0x000) 11#define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024) 12#define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028) 13#define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C) 14#define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108) 15#define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118) 16#define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C) 17#define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C) 18#define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460) 19 20/* BTINTEL_PCIE_CSR Function Control Register */ 21#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0)) 22#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6)) 23#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7)) 24#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) 25#define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31)) 26 27/* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ 28#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0)) 29#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1)) 30#define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) 31#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) 32#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) 33#define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) 34#define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23)) 35 36/* Registers for MSI-X */ 37#define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000) 38#define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800) 39#define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804) 40#define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808) 41#define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C) 42#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810) 43#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814) 44#define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880) 45#define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause)) 46 47/* Causes for the FH register interrupts */ 48enum msix_fh_int_causes { 49 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */ 50 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */ 51}; 52 53/* Causes for the HW register interrupts */ 54enum msix_hw_int_causes { 55 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */ 56}; 57 58#define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 59 60/* Minimum and Maximum number of MSI-X Vector 61 * Intel Bluetooth PCIe support only 1 vector 62 */ 63#define BTINTEL_PCIE_MSIX_VEC_MAX 1 64#define BTINTEL_PCIE_MSIX_VEC_MIN 1 65 66/* Default poll time for MAC access during init */ 67#define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000 68 69/* Default interrupt timeout in msec */ 70#define BTINTEL_DEFAULT_INTR_TIMEOUT 3000 71 72/* The number of descriptors in TX/RX queues */ 73#define BTINTEL_DESCS_COUNT 16 74 75/* Number of Queue for TX and RX 76 * It indicates the index of the IA(Index Array) 77 */ 78enum { 79 BTINTEL_PCIE_TXQ_NUM = 0, 80 BTINTEL_PCIE_RXQ_NUM = 1, 81 BTINTEL_PCIE_NUM_QUEUES = 2, 82}; 83 84/* The size of DMA buffer for TX and RX in bytes */ 85#define BTINTEL_PCIE_BUFFER_SIZE 4096 86 87/* DMA allocation alignment */ 88#define BTINTEL_PCIE_DMA_POOL_ALIGNMENT 256 89 90#define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500 91 92/* Doorbell vector for TFD */ 93#define BTINTEL_PCIE_TX_DB_VEC 0 94 95/* Number of pending RX requests for downlink */ 96#define BTINTEL_PCIE_RX_MAX_QUEUE 6 97 98/* Doorbell vector for FRBD */ 99#define BTINTEL_PCIE_RX_DB_VEC 513 100 101/* RBD buffer size mapping */ 102#define BTINTEL_PCIE_RBD_SIZE_4K 0x04 103 104/* 105 * Struct for Context Information (v2) 106 * 107 * All members are write-only for host and read-only for device. 108 * 109 * @version: Version of context information 110 * @size: Size of context information 111 * @config: Config with which host wants peripheral to execute 112 * Subset of capability register published by device 113 * @addr_tr_hia: Address of TR Head Index Array 114 * @addr_tr_tia: Address of TR Tail Index Array 115 * @addr_cr_hia: Address of CR Head Index Array 116 * @addr_cr_tia: Address of CR Tail Index Array 117 * @num_tr_ia: Number of entries in TR Index Arrays 118 * @num_cr_ia: Number of entries in CR Index Arrays 119 * @rbd_siz: RBD Size { 0x4=4K } 120 * @addr_tfdq: Address of TFD Queue(tx) 121 * @addr_urbdq0: Address of URBD Queue(tx) 122 * @num_tfdq: Number of TFD in TFD Queue(tx) 123 * @num_urbdq0: Number of URBD in URBD Queue(tx) 124 * @tfdq_db_vec: Queue number of TFD 125 * @urbdq0_db_vec: Queue number of URBD 126 * @addr_frbdq: Address of FRBD Queue(rx) 127 * @addr_urbdq1: Address of URBD Queue(rx) 128 * @num_frbdq: Number of FRBD in FRBD Queue(rx) 129 * @frbdq_db_vec: Queue number of FRBD 130 * @num_urbdq1: Number of URBD in URBD Queue(rx) 131 * @urbdq_db_vec: Queue number of URBDQ1 132 * @tr_msi_vec: Transfer Ring MSI-X Vector 133 * @cr_msi_vec: Completion Ring MSI-X Vector 134 * @dbgc_addr: DBGC first fragment address 135 * @dbgc_size: DBGC buffer size 136 * @early_enable: Enarly debug enable 137 * @dbg_output_mode: Debug output mode 138 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } 139 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } 140 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) 141 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } 142 * @dbg_preset: Debug preset 143 * @ext_addr: Address of context information extension 144 * @ext_size: Size of context information part 145 * 146 * Total 38 DWords 147 */ 148struct ctx_info { 149 u16 version; 150 u16 size; 151 u32 config; 152 u32 reserved_dw02; 153 u32 reserved_dw03; 154 u64 addr_tr_hia; 155 u64 addr_tr_tia; 156 u64 addr_cr_hia; 157 u64 addr_cr_tia; 158 u16 num_tr_ia; 159 u16 num_cr_ia; 160 u32 rbd_size:4, 161 reserved_dw13:28; 162 u64 addr_tfdq; 163 u64 addr_urbdq0; 164 u16 num_tfdq; 165 u16 num_urbdq0; 166 u16 tfdq_db_vec; 167 u16 urbdq0_db_vec; 168 u64 addr_frbdq; 169 u64 addr_urbdq1; 170 u16 num_frbdq; 171 u16 frbdq_db_vec; 172 u16 num_urbdq1; 173 u16 urbdq_db_vec; 174 u16 tr_msi_vec; 175 u16 cr_msi_vec; 176 u32 reserved_dw27; 177 u64 dbgc_addr; 178 u32 dbgc_size; 179 u32 early_enable:1, 180 reserved_dw31:3, 181 dbg_output_mode:4, 182 dbg_preset:8, 183 reserved2_dw31:16; 184 u64 ext_addr; 185 u32 ext_size; 186 u32 test_param; 187 u32 reserved_dw36; 188 u32 reserved_dw37; 189} __packed; 190 191/* Transfer Descriptor for TX 192 * @type: Not in use. Set to 0x0 193 * @size: Size of data in the buffer 194 * @addr: DMA Address of buffer 195 */ 196struct tfd { 197 u8 type; 198 u16 size; 199 u8 reserved; 200 u64 addr; 201 u32 reserved1; 202} __packed; 203 204/* URB Descriptor for TX 205 * @tfd_index: Index of TFD in TFDQ + 1 206 * @num_txq: Queue index of TFD Queue 207 * @cmpl_count: Completion count. Always 0x01 208 * @immediate_cmpl: Immediate completion flag: Always 0x01 209 */ 210struct urbd0 { 211 u32 tfd_index:16, 212 num_txq:8, 213 cmpl_count:4, 214 reserved:3, 215 immediate_cmpl:1; 216} __packed; 217 218/* FRB Descriptor for RX 219 * @tag: RX buffer tag (index of RX buffer queue) 220 * @addr: Address of buffer 221 */ 222struct frbd { 223 u32 tag:16, 224 reserved:16; 225 u32 reserved2; 226 u64 addr; 227} __packed; 228 229/* URB Descriptor for RX 230 * @frbd_tag: Tag from FRBD 231 * @status: Status 232 */ 233struct urbd1 { 234 u32 frbd_tag:16, 235 status:1, 236 reserved:14, 237 fixed:1; 238} __packed; 239 240/* RFH header in RX packet 241 * @packet_len: Length of the data in the buffer 242 * @rxq: RX Queue number 243 * @cmd_id: Command ID. Not in Use 244 */ 245struct rfh_hdr { 246 u64 packet_len:16, 247 rxq:6, 248 reserved:10, 249 cmd_id:16, 250 reserved1:16; 251} __packed; 252 253/* Internal data buffer 254 * @data: pointer to the data buffer 255 * @p_addr: physical address of data buffer 256 */ 257struct data_buf { 258 u8 *data; 259 dma_addr_t data_p_addr; 260}; 261 262/* Index Array */ 263struct ia { 264 dma_addr_t tr_hia_p_addr; 265 u16 *tr_hia; 266 dma_addr_t tr_tia_p_addr; 267 u16 *tr_tia; 268 dma_addr_t cr_hia_p_addr; 269 u16 *cr_hia; 270 dma_addr_t cr_tia_p_addr; 271 u16 *cr_tia; 272}; 273 274/* Structure for TX Queue 275 * @count: Number of descriptors 276 * @tfds: Array of TFD 277 * @urbd0s: Array of URBD0 278 * @buf: Array of data_buf structure 279 */ 280struct txq { 281 u16 count; 282 283 dma_addr_t tfds_p_addr; 284 struct tfd *tfds; 285 286 dma_addr_t urbd0s_p_addr; 287 struct urbd0 *urbd0s; 288 289 dma_addr_t buf_p_addr; 290 void *buf_v_addr; 291 struct data_buf *bufs; 292}; 293 294/* Structure for RX Queue 295 * @count: Number of descriptors 296 * @frbds: Array of FRBD 297 * @urbd1s: Array of URBD1 298 * @buf: Array of data_buf structure 299 */ 300struct rxq { 301 u16 count; 302 303 dma_addr_t frbds_p_addr; 304 struct frbd *frbds; 305 306 dma_addr_t urbd1s_p_addr; 307 struct urbd1 *urbd1s; 308 309 dma_addr_t buf_p_addr; 310 void *buf_v_addr; 311 struct data_buf *bufs; 312}; 313 314/* struct btintel_pcie_data 315 * @pdev: pci device 316 * @hdev: hdev device 317 * @flags: driver state 318 * @irq_lock: spinlock for MSI-X 319 * @hci_rx_lock: spinlock for HCI RX flow 320 * @base_addr: pci base address (from BAR) 321 * @msix_entries: array of MSI-X entries 322 * @msix_enabled: true if MSI-X is enabled; 323 * @alloc_vecs: number of interrupt vectors allocated 324 * @def_irq: default irq for all causes 325 * @fh_init_mask: initial unmasked rxq causes 326 * @hw_init_mask: initial unmaksed hw causes 327 * @boot_stage_cache: cached value of boot stage register 328 * @img_resp_cache: cached value of image response register 329 * @cnvi: CNVi register value 330 * @cnvr: CNVr register value 331 * @gp0_received: condition for gp0 interrupt 332 * @gp0_wait_q: wait_q for gp0 interrupt 333 * @tx_wait_done: condition for tx interrupt 334 * @tx_wait_q: wait_q for tx interrupt 335 * @workqueue: workqueue for RX work 336 * @rx_skb_q: SKB queue for RX packet 337 * @rx_work: RX work struct to process the RX packet in @rx_skb_q 338 * @dma_pool: DMA pool for descriptors, index array and ci 339 * @dma_p_addr: DMA address for pool 340 * @dma_v_addr: address of pool 341 * @ci_p_addr: DMA address for CI struct 342 * @ci: CI struct 343 * @ia: Index Array struct 344 * @txq: TX Queue struct 345 * @rxq: RX Queue struct 346 */ 347struct btintel_pcie_data { 348 struct pci_dev *pdev; 349 struct hci_dev *hdev; 350 351 unsigned long flags; 352 /* lock used in MSI-X interrupt */ 353 spinlock_t irq_lock; 354 /* lock to serialize rx events */ 355 spinlock_t hci_rx_lock; 356 357 void __iomem *base_addr; 358 359 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX]; 360 bool msix_enabled; 361 u32 alloc_vecs; 362 u32 def_irq; 363 364 u32 fh_init_mask; 365 u32 hw_init_mask; 366 367 u32 boot_stage_cache; 368 u32 img_resp_cache; 369 370 u32 cnvi; 371 u32 cnvr; 372 373 bool gp0_received; 374 wait_queue_head_t gp0_wait_q; 375 376 bool tx_wait_done; 377 wait_queue_head_t tx_wait_q; 378 379 struct workqueue_struct *workqueue; 380 struct sk_buff_head rx_skb_q; 381 struct work_struct rx_work; 382 383 struct dma_pool *dma_pool; 384 dma_addr_t dma_p_addr; 385 void *dma_v_addr; 386 387 dma_addr_t ci_p_addr; 388 struct ctx_info *ci; 389 struct ia ia; 390 struct txq txq; 391 struct rxq rxq; 392}; 393 394static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, 395 u32 offset) 396{ 397 return ioread32(data->base_addr + offset); 398} 399 400static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, 401 u32 offset, u8 val) 402{ 403 iowrite8(val, data->base_addr + offset); 404} 405 406static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, 407 u32 offset, u32 val) 408{ 409 iowrite32(val, data->base_addr + offset); 410} 411 412static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, 413 u32 offset, u32 bits) 414{ 415 u32 r; 416 417 r = ioread32(data->base_addr + offset); 418 r |= bits; 419 iowrite32(r, data->base_addr + offset); 420} 421 422static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, 423 u32 offset, u32 bits) 424{ 425 u32 r; 426 427 r = ioread32(data->base_addr + offset); 428 r &= ~bits; 429 iowrite32(r, data->base_addr + offset); 430} 431