1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * drivers/atm/suni.h - S/UNI PHY driver 4 */ 5 6/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 7 8#ifndef DRIVER_ATM_SUNI_H 9#define DRIVER_ATM_SUNI_H 10 11#include <linux/atmdev.h> 12#include <linux/atmioc.h> 13#include <linux/sonet.h> 14 15/* SUNI registers */ 16 17#define SUNI_MRI 0x00 /* Master Reset and Identity / Load 18 Meter */ 19#define SUNI_MC 0x01 /* Master Configuration */ 20#define SUNI_MIS 0x02 /* Master Interrupt Status */ 21 /* no 0x03 */ 22#define SUNI_MCM 0x04 /* Master Clock Monitor */ 23#define SUNI_MCT 0x05 /* Master Control */ 24#define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */ 25#define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */ 26 /* 0x08-0x0F reserved */ 27#define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */ 28#define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */ 29#define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */ 30#define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */ 31#define SUNI_TSOP_CTRL 0x14 /* TSOP Control */ 32#define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */ 33 /* 0x16-0x17 reserved */ 34#define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */ 35#define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */ 36#define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */ 37#define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */ 38#define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */ 39#define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */ 40#define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */ 41#define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */ 42#define SUNI_TLOP_CTRL 0x20 /* TLOP Control */ 43#define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */ 44 /* 0x22-0x27 reserved */ 45#define SUNI_SSTB_CTRL 0x28 46#define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */ 47#define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */ 48 /* 0x32 reserved */ 49#define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */ 50 /* 0x34-0x36 reserved */ 51#define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */ 52#define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */ 53#define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */ 54#define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */ 55#define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */ 56 /* 0x3C reserved */ 57#define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */ 58#define SUNI_RPOP_RC 0x3D /* RPOP Ring Control (PM5355) */ 59 /* 0x3E-0x3F reserved */ 60#define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */ 61#define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */ 62 /* 0x42-0x44 reserved */ 63#define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */ 64#define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */ 65 /* 0x47 reserved */ 66#define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */ 67#define SUNI_TPOP_PS 0x49 /* TPOP Path Status */ 68 /* 0x4A-0x4F reserved */ 69#define SUNI_RACP_CS 0x50 /* RACP Control/Status */ 70#define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */ 71#define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */ 72#define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */ 73#define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */ 74#define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */ 75#define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */ 76#define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */ 77#define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */ 78#define SUNI_RACP_CFG 0x59 /* RACP Configuration */ 79 /* 0x5A-0x5F reserved */ 80#define SUNI_TACP_CS 0x60 /* TACP Control/Status */ 81#define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */ 82#define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload 83 Octet Pattern */ 84#define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */ 85#define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */ 86#define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */ 87#define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */ 88#define SUNI_TACP_CFG 0x67 /* TACP Configuration */ 89#define SUNI_SPTB_CTRL 0x68 /* SPTB Control */ 90 /* 0x69-0x7F reserved */ 91#define SUNI_MT 0x80 /* Master Test */ 92 /* 0x81-0xFF reserved */ 93 94/* SUNI register values */ 95 96 97/* MRI is reg 0 */ 98#define SUNI_MRI_ID 0x0f /* R, SUNI revision number */ 99#define SUNI_MRI_ID_SHIFT 0 100#define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */ 101#define SUNI_MRI_TYPE_SHIFT 4 102#define SUNI_MRI_TYPE_PM5346 0x3 /* S/UNI 155 LITE */ 103#define SUNI_MRI_TYPE_PM5347 0x4 /* S/UNI 155 PLUS */ 104#define SUNI_MRI_TYPE_PM5350 0x7 /* S/UNI 155 ULTRA */ 105#define SUNI_MRI_TYPE_PM5355 0x1 /* S/UNI 622 */ 106#define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip 107 0: normal operation 108 1: reset & low power */ 109 110/* MCM is reg 0x4 */ 111#define SUNI_MCM_LLE 0x20 /* line loopback (PM5355) */ 112#define SUNI_MCM_DLE 0x10 /* diagnostic loopback (PM5355) */ 113 114/* MCT is reg 5 */ 115#define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from 116 TRCLK+/- */ 117#define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */ 118#define SUNI_MCT_LLE 0x04 /* RW, line loopback */ 119#define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer 120 adjustments 121 0: payload ptr controlled by TPOP 122 ptr control reg 123 1: payload pointer fixed at 522 */ 124#define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */ 125#define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation 126 interrupt (1: on) */ 127/* RSOP_CIE is reg 0x10 */ 128#define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm 129 state change */ 130#define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of 131 frame state change */ 132#define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of 133 signal state change */ 134#define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section 135 BIP-8 error (B1) */ 136#define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next 137 boundary */ 138#define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */ 139 140/* RSOP_SIS is reg 0x11 */ 141#define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */ 142#define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */ 143#define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */ 144#define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */ 145#define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */ 146#define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */ 147#define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */ 148 149/* TSOP_CTRL is reg 0x14 */ 150#define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */ 151#define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */ 152 153/* TSOP_DIAG is reg 0x15 */ 154#define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */ 155#define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */ 156#define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */ 157 158/* TLOP_DIAG is reg 0x21 */ 159#define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */ 160 161/* SSTB_CTRL is reg 0x28 */ 162#define SUNI_SSTB_CTRL_LEN16 0x01 /* path trace message length bit */ 163 164/* RPOP_RC is reg 0x3D (PM5355) */ 165#define SUNI_RPOP_RC_ENSS 0x40 /* enable size bit */ 166 167/* TPOP_DIAG is reg 0x40 */ 168#define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */ 169#define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */ 170 171/* TPOP_APM is reg 0x46 */ 172#define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2 173 bits */ 174#define SUNI_TPOP_APM_APTR_SHIFT 0 175#define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload 176 pointer */ 177#define SUNI_TPOP_APM_S_SHIFT 2 178#define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */ 179#define SUNI_TPOP_APM_NDF_SHIFT 4 180 181#define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */ 182#define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */ 183 184/* RACP_IES is reg 0x51 */ 185#define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */ 186#define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */ 187#define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */ 188#define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation 189 state */ 190#define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */ 191#define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */ 192#define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state 193 change interrupt */ 194 195/* TACP_CS is reg 0x60 */ 196#define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */ 197#define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */ 198#define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */ 199#define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */ 200#define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */ 201#define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */ 202#define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */ 203 204/* TACP_IUCHP is reg 0x61 */ 205#define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u 206 pattern */ 207#define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u 208 pattern */ 209#define SUNI_TACP_IUCHP_PTI_SHIFT 1 210#define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u 211 pattern */ 212#define SUNI_TACP_IUCHP_GFC_SHIFT 4 213 214/* SPTB_CTRL is reg 0x68 */ 215#define SUNI_SPTB_CTRL_LEN16 0x01 /* path trace message length */ 216 217/* MT is reg 0x80 */ 218#define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface 219 tri-state */ 220#define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */ 221#define SUNI_MT_IOTST 0x04 /* RW, enable test mode */ 222#define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */ 223#define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */ 224#define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */ 225 226 227#define SUNI_IDLE_PATTERN 0x6a /* idle pattern */ 228 229 230#ifdef __KERNEL__ 231struct suni_priv { 232 struct k_sonet_stats sonet_stats; /* link diagnostics */ 233 int loop_mode; /* loopback mode */ 234 int type; /* phy type */ 235 struct atm_dev *dev; /* device back-pointer */ 236 struct suni_priv *next; /* next SUNI */ 237}; 238 239int suni_init(struct atm_dev *dev); 240#endif 241 242#endif 243