1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ata_piix.c - Intel PATA/SATA controllers 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * Copyright header from piix.c: 13 * 14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 16 * Copyright (C) 2003 Red Hat Inc 17 * 18 * libata documentation is available via 'make {ps|pdf}docs', 19 * as Documentation/driver-api/libata.rst 20 * 21 * Hardware documentation available at http://developer.intel.com/ 22 * 23 * Documentation 24 * Publicly available from Intel web site. Errata documentation 25 * is also publicly available. As an aide to anyone hacking on this 26 * driver the list of errata that are relevant is below, going back to 27 * PIIX4. Older device documentation is now a bit tricky to find. 28 * 29 * The chipsets all follow very much the same design. The original Triton 30 * series chipsets do _not_ support independent device timings, but this 31 * is fixed in Triton II. With the odd mobile exception the chips then 32 * change little except in gaining more modes until SATA arrives. This 33 * driver supports only the chips with independent timing (that is those 34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 35 * for the early chip drivers. 36 * 37 * Errata of note: 38 * 39 * Unfixable 40 * PIIX4 errata #9 - Only on ultra obscure hw 41 * ICH3 errata #13 - Not observed to affect real hw 42 * by Intel 43 * 44 * Things we must deal with 45 * PIIX4 errata #10 - BM IDE hang with non UDMA 46 * (must stop/start dma to recover) 47 * 440MX errata #15 - As PIIX4 errata #10 48 * PIIX4 errata #15 - Must not read control registers 49 * during a PIO transfer 50 * 440MX errata #13 - As PIIX4 errata #15 51 * ICH2 errata #21 - DMA mode 0 doesn't work right 52 * ICH0/1 errata #55 - As ICH2 errata #21 53 * ICH2 spec c #9 - Extra operations needed to handle 54 * drive hotswap [NOT YET SUPPORTED] 55 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 56 * and must be dword aligned 57 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 58 * ICH7 errata #16 - MWDMA1 timings are incorrect 59 * 60 * Should have been BIOS fixed: 61 * 450NX: errata #19 - DMA hangs on old 450NX 62 * 450NX: errata #20 - DMA hangs on old 450NX 63 * 450NX: errata #25 - Corruption with DMA on old 450NX 64 * ICH3 errata #15 - IDE deadlock under high load 65 * (BIOS must set dev 31 fn 0 bit 23) 66 * ICH3 errata #18 - Don't use native mode 67 */ 68 69#include <linux/kernel.h> 70#include <linux/module.h> 71#include <linux/pci.h> 72#include <linux/init.h> 73#include <linux/blkdev.h> 74#include <linux/delay.h> 75#include <linux/device.h> 76#include <linux/gfp.h> 77#include <scsi/scsi_host.h> 78#include <linux/libata.h> 79#include <linux/dmi.h> 80#include <trace/events/libata.h> 81 82#define DRV_NAME "ata_piix" 83#define DRV_VERSION "2.13" 84 85enum { 86 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 87 ICH5_PMR = 0x90, /* address map register */ 88 ICH5_PCS = 0x92, /* port control and status */ 89 PIIX_SIDPR_BAR = 5, 90 PIIX_SIDPR_LEN = 16, 91 PIIX_SIDPR_IDX = 0, 92 PIIX_SIDPR_DATA = 4, 93 94 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 95 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 96 97 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 98 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 99 100 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/ 101 102 PIIX_80C_PRI = (1 << 5) | (1 << 4), 103 PIIX_80C_SEC = (1 << 7) | (1 << 6), 104 105 /* constants for mapping table */ 106 P0 = 0, /* port 0 */ 107 P1 = 1, /* port 1 */ 108 P2 = 2, /* port 2 */ 109 P3 = 3, /* port 3 */ 110 IDE = -1, /* IDE */ 111 NA = -2, /* not available */ 112 RV = -3, /* reserved */ 113 114 PIIX_AHCI_DEVICE = 6, 115 116 /* host->flags bits */ 117 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 118}; 119 120enum piix_controller_ids { 121 /* controller IDs */ 122 piix_pata_mwdma, /* PIIX3 MWDMA only */ 123 piix_pata_33, /* PIIX4 at 33Mhz */ 124 ich_pata_33, /* ICH up to UDMA 33 only */ 125 ich_pata_66, /* ICH up to 66 Mhz */ 126 ich_pata_100, /* ICH up to UDMA 100 */ 127 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 128 ich5_sata, 129 ich6_sata, 130 ich6m_sata, 131 ich8_sata, 132 ich8_2port_sata, 133 ich8m_apple_sata, /* locks up on second port enable */ 134 tolapai_sata, 135 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 136 ich8_sata_snb, 137 ich8_2port_sata_snb, 138 ich8_2port_sata_byt, 139}; 140 141struct piix_map_db { 142 const u32 mask; 143 const u16 port_enable; 144 const int map[][4]; 145}; 146 147struct piix_host_priv { 148 const int *map; 149 u32 saved_iocfg; 150 void __iomem *sidpr; 151}; 152 153static unsigned int in_module_init = 1; 154 155static const struct pci_device_id piix_pci_tbl[] = { 156 /* Intel PIIX3 for the 430HX etc */ 157 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 158 /* VMware ICH4 */ 159 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 160 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 161 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 162 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 163 /* Intel PIIX4 */ 164 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 165 /* Intel PIIX4 */ 166 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 167 /* Intel PIIX */ 168 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 169 /* Intel ICH (i810, i815, i840) UDMA 66*/ 170 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 171 /* Intel ICH0 : UDMA 33*/ 172 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 173 /* Intel ICH2M */ 174 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 175 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 176 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 177 /* Intel ICH3M */ 178 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 179 /* Intel ICH3 (E7500/1) UDMA 100 */ 180 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 181 /* Intel ICH4-L */ 182 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 183 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 184 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 185 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 186 /* Intel ICH5 */ 187 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 188 /* C-ICH (i810E2) */ 189 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 190 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 191 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 192 /* ICH6 (and 6) (i915) UDMA 100 */ 193 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 194 /* ICH7/7-R (i945, i975) UDMA 100*/ 195 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 196 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 197 /* ICH8 Mobile PATA Controller */ 198 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 199 200 /* SATA ports */ 201 202 /* 82801EB (ICH5) */ 203 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 204 /* 82801EB (ICH5) */ 205 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 206 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 207 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 208 /* 6300ESB pretending RAID */ 209 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 210 /* 82801FB/FW (ICH6/ICH6W) */ 211 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 212 /* 82801FR/FRW (ICH6R/ICH6RW) */ 213 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 214 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 215 * Attach iff the controller is in IDE mode. */ 216 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 217 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 218 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 219 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 220 /* 82801GBM/GHM (ICH7M, identical to ICH6M) */ 221 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 222 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 223 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 224 /* SATA Controller 1 IDE (ICH8) */ 225 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 226 /* SATA Controller 2 IDE (ICH8) */ 227 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 228 /* Mobile SATA Controller IDE (ICH8M), Apple */ 229 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 230 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 231 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 232 /* Mobile SATA Controller IDE (ICH8M) */ 233 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 234 /* SATA Controller IDE (ICH9) */ 235 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 236 /* SATA Controller IDE (ICH9) */ 237 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 238 /* SATA Controller IDE (ICH9) */ 239 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 240 /* SATA Controller IDE (ICH9M) */ 241 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 242 /* SATA Controller IDE (ICH9M) */ 243 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 244 /* SATA Controller IDE (ICH9M) */ 245 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 246 /* SATA Controller IDE (Tolapai) */ 247 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 248 /* SATA Controller IDE (ICH10) */ 249 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 250 /* SATA Controller IDE (ICH10) */ 251 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 252 /* SATA Controller IDE (ICH10) */ 253 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 254 /* SATA Controller IDE (ICH10) */ 255 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 256 /* SATA Controller IDE (PCH) */ 257 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 258 /* SATA Controller IDE (PCH) */ 259 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 260 /* SATA Controller IDE (PCH) */ 261 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 262 /* SATA Controller IDE (PCH) */ 263 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 264 /* SATA Controller IDE (PCH) */ 265 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 266 /* SATA Controller IDE (PCH) */ 267 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 268 /* SATA Controller IDE (CPT) */ 269 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 270 /* SATA Controller IDE (CPT) */ 271 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 272 /* SATA Controller IDE (CPT) */ 273 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 274 /* SATA Controller IDE (CPT) */ 275 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 276 /* SATA Controller IDE (PBG) */ 277 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 278 /* SATA Controller IDE (PBG) */ 279 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 280 /* SATA Controller IDE (Panther Point) */ 281 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 282 /* SATA Controller IDE (Panther Point) */ 283 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 284 /* SATA Controller IDE (Panther Point) */ 285 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 286 /* SATA Controller IDE (Panther Point) */ 287 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 288 /* SATA Controller IDE (Lynx Point) */ 289 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 290 /* SATA Controller IDE (Lynx Point) */ 291 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 292 /* SATA Controller IDE (Lynx Point) */ 293 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 294 /* SATA Controller IDE (Lynx Point) */ 295 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 296 /* SATA Controller IDE (Lynx Point-LP) */ 297 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 298 /* SATA Controller IDE (Lynx Point-LP) */ 299 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 300 /* SATA Controller IDE (Lynx Point-LP) */ 301 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 302 /* SATA Controller IDE (Lynx Point-LP) */ 303 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 304 /* SATA Controller IDE (DH89xxCC) */ 305 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 306 /* SATA Controller IDE (Avoton) */ 307 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 308 /* SATA Controller IDE (Avoton) */ 309 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 310 /* SATA Controller IDE (Avoton) */ 311 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 312 /* SATA Controller IDE (Avoton) */ 313 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 314 /* SATA Controller IDE (Wellsburg) */ 315 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 316 /* SATA Controller IDE (Wellsburg) */ 317 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 318 /* SATA Controller IDE (Wellsburg) */ 319 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 320 /* SATA Controller IDE (Wellsburg) */ 321 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 322 /* SATA Controller IDE (BayTrail) */ 323 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt }, 324 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt }, 325 /* SATA Controller IDE (Coleto Creek) */ 326 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 327 /* SATA Controller IDE (9 Series) */ 328 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 329 /* SATA Controller IDE (9 Series) */ 330 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 331 /* SATA Controller IDE (9 Series) */ 332 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 333 /* SATA Controller IDE (9 Series) */ 334 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 335 336 { } /* terminate list */ 337}; 338 339static const struct piix_map_db ich5_map_db = { 340 .mask = 0x7, 341 .port_enable = 0x3, 342 .map = { 343 /* PM PS SM SS MAP */ 344 { P0, NA, P1, NA }, /* 000b */ 345 { P1, NA, P0, NA }, /* 001b */ 346 { RV, RV, RV, RV }, 347 { RV, RV, RV, RV }, 348 { P0, P1, IDE, IDE }, /* 100b */ 349 { P1, P0, IDE, IDE }, /* 101b */ 350 { IDE, IDE, P0, P1 }, /* 110b */ 351 { IDE, IDE, P1, P0 }, /* 111b */ 352 }, 353}; 354 355static const struct piix_map_db ich6_map_db = { 356 .mask = 0x3, 357 .port_enable = 0xf, 358 .map = { 359 /* PM PS SM SS MAP */ 360 { P0, P2, P1, P3 }, /* 00b */ 361 { IDE, IDE, P1, P3 }, /* 01b */ 362 { P0, P2, IDE, IDE }, /* 10b */ 363 { RV, RV, RV, RV }, 364 }, 365}; 366 367static const struct piix_map_db ich6m_map_db = { 368 .mask = 0x3, 369 .port_enable = 0x5, 370 371 /* Map 01b isn't specified in the doc but some notebooks use 372 * it anyway. MAP 01b have been spotted on both ICH6M and 373 * ICH7M. 374 */ 375 .map = { 376 /* PM PS SM SS MAP */ 377 { P0, P2, NA, NA }, /* 00b */ 378 { IDE, IDE, P1, P3 }, /* 01b */ 379 { P0, P2, IDE, IDE }, /* 10b */ 380 { RV, RV, RV, RV }, 381 }, 382}; 383 384static const struct piix_map_db ich8_map_db = { 385 .mask = 0x3, 386 .port_enable = 0xf, 387 .map = { 388 /* PM PS SM SS MAP */ 389 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 390 { RV, RV, RV, RV }, 391 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 392 { RV, RV, RV, RV }, 393 }, 394}; 395 396static const struct piix_map_db ich8_2port_map_db = { 397 .mask = 0x3, 398 .port_enable = 0x3, 399 .map = { 400 /* PM PS SM SS MAP */ 401 { P0, NA, P1, NA }, /* 00b */ 402 { RV, RV, RV, RV }, /* 01b */ 403 { RV, RV, RV, RV }, /* 10b */ 404 { RV, RV, RV, RV }, 405 }, 406}; 407 408static const struct piix_map_db ich8m_apple_map_db = { 409 .mask = 0x3, 410 .port_enable = 0x1, 411 .map = { 412 /* PM PS SM SS MAP */ 413 { P0, NA, NA, NA }, /* 00b */ 414 { RV, RV, RV, RV }, 415 { P0, P2, IDE, IDE }, /* 10b */ 416 { RV, RV, RV, RV }, 417 }, 418}; 419 420static const struct piix_map_db tolapai_map_db = { 421 .mask = 0x3, 422 .port_enable = 0x3, 423 .map = { 424 /* PM PS SM SS MAP */ 425 { P0, NA, P1, NA }, /* 00b */ 426 { RV, RV, RV, RV }, /* 01b */ 427 { RV, RV, RV, RV }, /* 10b */ 428 { RV, RV, RV, RV }, 429 }, 430}; 431 432static const struct piix_map_db *piix_map_db_table[] = { 433 [ich5_sata] = &ich5_map_db, 434 [ich6_sata] = &ich6_map_db, 435 [ich6m_sata] = &ich6m_map_db, 436 [ich8_sata] = &ich8_map_db, 437 [ich8_2port_sata] = &ich8_2port_map_db, 438 [ich8m_apple_sata] = &ich8m_apple_map_db, 439 [tolapai_sata] = &tolapai_map_db, 440 [ich8_sata_snb] = &ich8_map_db, 441 [ich8_2port_sata_snb] = &ich8_2port_map_db, 442 [ich8_2port_sata_byt] = &ich8_2port_map_db, 443}; 444 445static const struct pci_bits piix_enable_bits[] = { 446 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 447 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 448}; 449 450MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 451MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 452MODULE_LICENSE("GPL"); 453MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 454MODULE_VERSION(DRV_VERSION); 455 456struct ich_laptop { 457 u16 device; 458 u16 subvendor; 459 u16 subdevice; 460}; 461 462/* 463 * List of laptops that use short cables rather than 80 wire 464 */ 465 466static const struct ich_laptop ich_laptop[] = { 467 /* devid, subvendor, subdev */ 468 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 469 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 470 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 471 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ 472 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 473 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 474 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ 475 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 476 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ 477 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 478 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 479 { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */ 480 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 481 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 482 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 483 /* end marker */ 484 { 0, } 485}; 486 487static int piix_port_start(struct ata_port *ap) 488{ 489 if (!(ap->flags & PIIX_FLAG_PIO16)) 490 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; 491 492 return ata_bmdma_port_start(ap); 493} 494 495/** 496 * ich_pata_cable_detect - Probe host controller cable detect info 497 * @ap: Port for which cable detect info is desired 498 * 499 * Read 80c cable indicator from ATA PCI device's PCI config 500 * register. This register is normally set by firmware (BIOS). 501 * 502 * LOCKING: 503 * None (inherited from caller). 504 */ 505 506static int ich_pata_cable_detect(struct ata_port *ap) 507{ 508 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 509 struct piix_host_priv *hpriv = ap->host->private_data; 510 const struct ich_laptop *lap = &ich_laptop[0]; 511 u8 mask; 512 513 /* Check for specials */ 514 while (lap->device) { 515 if (lap->device == pdev->device && 516 lap->subvendor == pdev->subsystem_vendor && 517 lap->subdevice == pdev->subsystem_device) 518 return ATA_CBL_PATA40_SHORT; 519 520 lap++; 521 } 522 523 /* check BIOS cable detect results */ 524 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 525 if ((hpriv->saved_iocfg & mask) == 0) 526 return ATA_CBL_PATA40; 527 return ATA_CBL_PATA80; 528} 529 530/** 531 * piix_pata_prereset - prereset for PATA host controller 532 * @link: Target link 533 * @deadline: deadline jiffies for the operation 534 * 535 * LOCKING: 536 * None (inherited from caller). 537 */ 538static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 539{ 540 struct ata_port *ap = link->ap; 541 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 542 543 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 544 return -ENOENT; 545 return ata_sff_prereset(link, deadline); 546} 547 548static DEFINE_SPINLOCK(piix_lock); 549 550static void piix_set_timings(struct ata_port *ap, struct ata_device *adev, 551 u8 pio) 552{ 553 struct pci_dev *dev = to_pci_dev(ap->host->dev); 554 unsigned long flags; 555 unsigned int is_slave = (adev->devno != 0); 556 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 557 unsigned int slave_port = 0x44; 558 u16 master_data; 559 u8 slave_data; 560 u8 udma_enable; 561 int control = 0; 562 563 /* 564 * See Intel Document 298600-004 for the timing programing rules 565 * for ICH controllers. 566 */ 567 568 static const /* ISP RTC */ 569 u8 timings[][2] = { { 0, 0 }, 570 { 0, 0 }, 571 { 1, 0 }, 572 { 2, 1 }, 573 { 2, 3 }, }; 574 575 if (pio >= 2) 576 control |= 1; /* TIME1 enable */ 577 if (ata_pio_need_iordy(adev)) 578 control |= 2; /* IE enable */ 579 /* Intel specifies that the PPE functionality is for disk only */ 580 if (adev->class == ATA_DEV_ATA) 581 control |= 4; /* PPE enable */ 582 /* 583 * If the drive MWDMA is faster than it can do PIO then 584 * we must force PIO into PIO0 585 */ 586 if (adev->pio_mode < XFER_PIO_0 + pio) 587 /* Enable DMA timing only */ 588 control |= 8; /* PIO cycles in PIO0 */ 589 590 spin_lock_irqsave(&piix_lock, flags); 591 592 /* PIO configuration clears DTE unconditionally. It will be 593 * programmed in set_dmamode which is guaranteed to be called 594 * after set_piomode if any DMA mode is available. 595 */ 596 pci_read_config_word(dev, master_port, &master_data); 597 if (is_slave) { 598 /* clear TIME1|IE1|PPE1|DTE1 */ 599 master_data &= 0xff0f; 600 /* enable PPE1, IE1 and TIME1 as needed */ 601 master_data |= (control << 4); 602 pci_read_config_byte(dev, slave_port, &slave_data); 603 slave_data &= (ap->port_no ? 0x0f : 0xf0); 604 /* Load the timing nibble for this slave */ 605 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 606 << (ap->port_no ? 4 : 0); 607 } else { 608 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 609 master_data &= 0xccf0; 610 /* Enable PPE, IE and TIME as appropriate */ 611 master_data |= control; 612 /* load ISP and RCT */ 613 master_data |= 614 (timings[pio][0] << 12) | 615 (timings[pio][1] << 8); 616 } 617 618 /* Enable SITRE (separate slave timing register) */ 619 master_data |= 0x4000; 620 pci_write_config_word(dev, master_port, master_data); 621 if (is_slave) 622 pci_write_config_byte(dev, slave_port, slave_data); 623 624 /* Ensure the UDMA bit is off - it will be turned back on if 625 UDMA is selected */ 626 627 if (ap->udma_mask) { 628 pci_read_config_byte(dev, 0x48, &udma_enable); 629 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 630 pci_write_config_byte(dev, 0x48, udma_enable); 631 } 632 633 spin_unlock_irqrestore(&piix_lock, flags); 634} 635 636/** 637 * piix_set_piomode - Initialize host controller PATA PIO timings 638 * @ap: Port whose timings we are configuring 639 * @adev: Drive in question 640 * 641 * Set PIO mode for device, in host controller PCI config space. 642 * 643 * LOCKING: 644 * None (inherited from caller). 645 */ 646 647static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 648{ 649 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0); 650} 651 652/** 653 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 654 * @ap: Port whose timings we are configuring 655 * @adev: Drive in question 656 * @isich: set if the chip is an ICH device 657 * 658 * Set UDMA mode for device, in host controller PCI config space. 659 * 660 * LOCKING: 661 * None (inherited from caller). 662 */ 663 664static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 665{ 666 struct pci_dev *dev = to_pci_dev(ap->host->dev); 667 unsigned long flags; 668 u8 speed = adev->dma_mode; 669 int devid = adev->devno + 2 * ap->port_no; 670 u8 udma_enable = 0; 671 672 if (speed >= XFER_UDMA_0) { 673 unsigned int udma = speed - XFER_UDMA_0; 674 u16 udma_timing; 675 u16 ideconf; 676 int u_clock, u_speed; 677 678 spin_lock_irqsave(&piix_lock, flags); 679 680 pci_read_config_byte(dev, 0x48, &udma_enable); 681 682 /* 683 * UDMA is handled by a combination of clock switching and 684 * selection of dividers 685 * 686 * Handy rule: Odd modes are UDMATIMx 01, even are 02 687 * except UDMA0 which is 00 688 */ 689 u_speed = min(2 - (udma & 1), udma); 690 if (udma == 5) 691 u_clock = 0x1000; /* 100Mhz */ 692 else if (udma > 2) 693 u_clock = 1; /* 66Mhz */ 694 else 695 u_clock = 0; /* 33Mhz */ 696 697 udma_enable |= (1 << devid); 698 699 /* Load the CT/RP selection */ 700 pci_read_config_word(dev, 0x4A, &udma_timing); 701 udma_timing &= ~(3 << (4 * devid)); 702 udma_timing |= u_speed << (4 * devid); 703 pci_write_config_word(dev, 0x4A, udma_timing); 704 705 if (isich) { 706 /* Select a 33/66/100Mhz clock */ 707 pci_read_config_word(dev, 0x54, &ideconf); 708 ideconf &= ~(0x1001 << devid); 709 ideconf |= u_clock << devid; 710 /* For ICH or later we should set bit 10 for better 711 performance (WR_PingPong_En) */ 712 pci_write_config_word(dev, 0x54, ideconf); 713 } 714 715 pci_write_config_byte(dev, 0x48, udma_enable); 716 717 spin_unlock_irqrestore(&piix_lock, flags); 718 } else { 719 /* MWDMA is driven by the PIO timings. */ 720 unsigned int mwdma = speed - XFER_MW_DMA_0; 721 const unsigned int needed_pio[3] = { 722 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 723 }; 724 int pio = needed_pio[mwdma] - XFER_PIO_0; 725 726 /* XFER_PIO_0 is never used currently */ 727 piix_set_timings(ap, adev, pio); 728 } 729} 730 731/** 732 * piix_set_dmamode - Initialize host controller PATA DMA timings 733 * @ap: Port whose timings we are configuring 734 * @adev: um 735 * 736 * Set MW/UDMA mode for device, in host controller PCI config space. 737 * 738 * LOCKING: 739 * None (inherited from caller). 740 */ 741 742static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 743{ 744 do_pata_set_dmamode(ap, adev, 0); 745} 746 747/** 748 * ich_set_dmamode - Initialize host controller PATA DMA timings 749 * @ap: Port whose timings we are configuring 750 * @adev: um 751 * 752 * Set MW/UDMA mode for device, in host controller PCI config space. 753 * 754 * LOCKING: 755 * None (inherited from caller). 756 */ 757 758static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 759{ 760 do_pata_set_dmamode(ap, adev, 1); 761} 762 763/* 764 * Serial ATA Index/Data Pair Superset Registers access 765 * 766 * Beginning from ICH8, there's a sane way to access SCRs using index 767 * and data register pair located at BAR5 which means that we have 768 * separate SCRs for master and slave. This is handled using libata 769 * slave_link facility. 770 */ 771static const int piix_sidx_map[] = { 772 [SCR_STATUS] = 0, 773 [SCR_ERROR] = 2, 774 [SCR_CONTROL] = 1, 775}; 776 777static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 778{ 779 struct ata_port *ap = link->ap; 780 struct piix_host_priv *hpriv = ap->host->private_data; 781 782 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 783 hpriv->sidpr + PIIX_SIDPR_IDX); 784} 785 786static int piix_sidpr_scr_read(struct ata_link *link, 787 unsigned int reg, u32 *val) 788{ 789 struct piix_host_priv *hpriv = link->ap->host->private_data; 790 791 if (reg >= ARRAY_SIZE(piix_sidx_map)) 792 return -EINVAL; 793 794 piix_sidpr_sel(link, reg); 795 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 796 return 0; 797} 798 799static int piix_sidpr_scr_write(struct ata_link *link, 800 unsigned int reg, u32 val) 801{ 802 struct piix_host_priv *hpriv = link->ap->host->private_data; 803 804 if (reg >= ARRAY_SIZE(piix_sidx_map)) 805 return -EINVAL; 806 807 piix_sidpr_sel(link, reg); 808 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 809 return 0; 810} 811 812static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 813 unsigned hints) 814{ 815 return sata_link_scr_lpm(link, policy, false); 816} 817 818static bool piix_irq_check(struct ata_port *ap) 819{ 820 unsigned char host_stat; 821 822 if (unlikely(!ap->ioaddr.bmdma_addr)) 823 return false; 824 825 host_stat = ap->ops->bmdma_status(ap); 826 trace_ata_bmdma_status(ap, host_stat); 827 828 return host_stat & ATA_DMA_INTR; 829} 830 831#ifdef CONFIG_PM_SLEEP 832static int piix_broken_suspend(void) 833{ 834 static const struct dmi_system_id sysids[] = { 835 { 836 .ident = "TECRA M3", 837 .matches = { 838 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 839 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 840 }, 841 }, 842 { 843 .ident = "TECRA M3", 844 .matches = { 845 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 846 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 847 }, 848 }, 849 { 850 .ident = "TECRA M3", 851 .matches = { 852 DMI_MATCH(DMI_OEM_STRING, "Tecra M3,"), 853 }, 854 }, 855 { 856 .ident = "TECRA M4", 857 .matches = { 858 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 859 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 860 }, 861 }, 862 { 863 .ident = "TECRA M4", 864 .matches = { 865 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 866 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 867 }, 868 }, 869 { 870 .ident = "TECRA M5", 871 .matches = { 872 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 873 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 874 }, 875 }, 876 { 877 .ident = "TECRA M6", 878 .matches = { 879 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 880 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 881 }, 882 }, 883 { 884 .ident = "TECRA M7", 885 .matches = { 886 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 887 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 888 }, 889 }, 890 { 891 .ident = "TECRA A8", 892 .matches = { 893 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 894 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 895 }, 896 }, 897 { 898 .ident = "Satellite R20", 899 .matches = { 900 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 901 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 902 }, 903 }, 904 { 905 .ident = "Satellite R25", 906 .matches = { 907 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 908 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 909 }, 910 }, 911 { 912 .ident = "Satellite U200", 913 .matches = { 914 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 915 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 916 }, 917 }, 918 { 919 .ident = "Satellite U200", 920 .matches = { 921 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 922 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 923 }, 924 }, 925 { 926 .ident = "Satellite Pro U200", 927 .matches = { 928 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 929 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 930 }, 931 }, 932 { 933 .ident = "Satellite U205", 934 .matches = { 935 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 936 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 937 }, 938 }, 939 { 940 .ident = "SATELLITE U205", 941 .matches = { 942 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 943 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 944 }, 945 }, 946 { 947 .ident = "Satellite Pro A120", 948 .matches = { 949 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 950 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"), 951 }, 952 }, 953 { 954 .ident = "Portege M500", 955 .matches = { 956 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 957 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 958 }, 959 }, 960 { 961 .ident = "VGN-BX297XP", 962 .matches = { 963 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 964 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 965 }, 966 }, 967 968 { } /* terminate list */ 969 }; 970 971 if (dmi_check_system(sysids)) 972 return 1; 973 974 /* TECRA M4 sometimes forgets its identify and reports bogus 975 * DMI information. As the bogus information is a bit 976 * generic, match as many entries as possible. This manual 977 * matching is necessary because dmi_system_id.matches is 978 * limited to four entries. 979 */ 980 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 981 dmi_match(DMI_PRODUCT_NAME, "000000") && 982 dmi_match(DMI_PRODUCT_VERSION, "000000") && 983 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 984 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 985 dmi_match(DMI_BOARD_NAME, "Portable PC") && 986 dmi_match(DMI_BOARD_VERSION, "Version A0")) 987 return 1; 988 989 return 0; 990} 991 992static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 993{ 994 struct ata_host *host = pci_get_drvdata(pdev); 995 unsigned long flags; 996 997 ata_host_suspend(host, mesg); 998 999 /* Some braindamaged ACPI suspend implementations expect the 1000 * controller to be awake on entry; otherwise, it burns cpu 1001 * cycles and power trying to do something to the sleeping 1002 * beauty. 1003 */ 1004 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1005 pci_save_state(pdev); 1006 1007 /* mark its power state as "unknown", since we don't 1008 * know if e.g. the BIOS will change its device state 1009 * when we suspend. 1010 */ 1011 if (pdev->current_state == PCI_D0) 1012 pdev->current_state = PCI_UNKNOWN; 1013 1014 /* tell resume that it's waking up from broken suspend */ 1015 spin_lock_irqsave(&host->lock, flags); 1016 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1017 spin_unlock_irqrestore(&host->lock, flags); 1018 } else 1019 ata_pci_device_do_suspend(pdev, mesg); 1020 1021 return 0; 1022} 1023 1024static int piix_pci_device_resume(struct pci_dev *pdev) 1025{ 1026 struct ata_host *host = pci_get_drvdata(pdev); 1027 unsigned long flags; 1028 int rc; 1029 1030 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1031 spin_lock_irqsave(&host->lock, flags); 1032 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1033 spin_unlock_irqrestore(&host->lock, flags); 1034 1035 pci_set_power_state(pdev, PCI_D0); 1036 pci_restore_state(pdev); 1037 1038 /* PCI device wasn't disabled during suspend. Use 1039 * pci_reenable_device() to avoid affecting the enable 1040 * count. 1041 */ 1042 rc = pci_reenable_device(pdev); 1043 if (rc) 1044 dev_err(&pdev->dev, 1045 "failed to enable device after resume (%d)\n", 1046 rc); 1047 } else 1048 rc = ata_pci_device_do_resume(pdev); 1049 1050 if (rc == 0) 1051 ata_host_resume(host); 1052 1053 return rc; 1054} 1055#endif 1056 1057static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1058{ 1059 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1060} 1061 1062static const struct scsi_host_template piix_sht = { 1063 ATA_BMDMA_SHT(DRV_NAME), 1064}; 1065 1066static struct ata_port_operations piix_sata_ops = { 1067 .inherits = &ata_bmdma32_port_ops, 1068 .sff_irq_check = piix_irq_check, 1069 .port_start = piix_port_start, 1070}; 1071 1072static struct ata_port_operations piix_pata_ops = { 1073 .inherits = &piix_sata_ops, 1074 .cable_detect = ata_cable_40wire, 1075 .set_piomode = piix_set_piomode, 1076 .set_dmamode = piix_set_dmamode, 1077 .prereset = piix_pata_prereset, 1078}; 1079 1080static struct ata_port_operations piix_vmw_ops = { 1081 .inherits = &piix_pata_ops, 1082 .bmdma_status = piix_vmw_bmdma_status, 1083}; 1084 1085static struct ata_port_operations ich_pata_ops = { 1086 .inherits = &piix_pata_ops, 1087 .cable_detect = ich_pata_cable_detect, 1088 .set_dmamode = ich_set_dmamode, 1089}; 1090 1091static struct attribute *piix_sidpr_shost_attrs[] = { 1092 &dev_attr_link_power_management_policy.attr, 1093 NULL 1094}; 1095 1096ATTRIBUTE_GROUPS(piix_sidpr_shost); 1097 1098static const struct scsi_host_template piix_sidpr_sht = { 1099 ATA_BMDMA_SHT(DRV_NAME), 1100 .shost_groups = piix_sidpr_shost_groups, 1101}; 1102 1103static struct ata_port_operations piix_sidpr_sata_ops = { 1104 .inherits = &piix_sata_ops, 1105 .hardreset = sata_std_hardreset, 1106 .scr_read = piix_sidpr_scr_read, 1107 .scr_write = piix_sidpr_scr_write, 1108 .set_lpm = piix_sidpr_set_lpm, 1109}; 1110 1111static struct ata_port_info piix_port_info[] = { 1112 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 1113 { 1114 .flags = PIIX_PATA_FLAGS, 1115 .pio_mask = ATA_PIO4, 1116 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1117 .port_ops = &piix_pata_ops, 1118 }, 1119 1120 [piix_pata_33] = /* PIIX4 at 33MHz */ 1121 { 1122 .flags = PIIX_PATA_FLAGS, 1123 .pio_mask = ATA_PIO4, 1124 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1125 .udma_mask = ATA_UDMA2, 1126 .port_ops = &piix_pata_ops, 1127 }, 1128 1129 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 1130 { 1131 .flags = PIIX_PATA_FLAGS, 1132 .pio_mask = ATA_PIO4, 1133 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 1134 .udma_mask = ATA_UDMA2, 1135 .port_ops = &ich_pata_ops, 1136 }, 1137 1138 [ich_pata_66] = /* ICH controllers up to 66MHz */ 1139 { 1140 .flags = PIIX_PATA_FLAGS, 1141 .pio_mask = ATA_PIO4, 1142 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 1143 .udma_mask = ATA_UDMA4, 1144 .port_ops = &ich_pata_ops, 1145 }, 1146 1147 [ich_pata_100] = 1148 { 1149 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1150 .pio_mask = ATA_PIO4, 1151 .mwdma_mask = ATA_MWDMA12_ONLY, 1152 .udma_mask = ATA_UDMA5, 1153 .port_ops = &ich_pata_ops, 1154 }, 1155 1156 [ich_pata_100_nomwdma1] = 1157 { 1158 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1159 .pio_mask = ATA_PIO4, 1160 .mwdma_mask = ATA_MWDMA2_ONLY, 1161 .udma_mask = ATA_UDMA5, 1162 .port_ops = &ich_pata_ops, 1163 }, 1164 1165 [ich5_sata] = 1166 { 1167 .flags = PIIX_SATA_FLAGS, 1168 .pio_mask = ATA_PIO4, 1169 .mwdma_mask = ATA_MWDMA2, 1170 .udma_mask = ATA_UDMA6, 1171 .port_ops = &piix_sata_ops, 1172 }, 1173 1174 [ich6_sata] = 1175 { 1176 .flags = PIIX_SATA_FLAGS, 1177 .pio_mask = ATA_PIO4, 1178 .mwdma_mask = ATA_MWDMA2, 1179 .udma_mask = ATA_UDMA6, 1180 .port_ops = &piix_sata_ops, 1181 }, 1182 1183 [ich6m_sata] = 1184 { 1185 .flags = PIIX_SATA_FLAGS, 1186 .pio_mask = ATA_PIO4, 1187 .mwdma_mask = ATA_MWDMA2, 1188 .udma_mask = ATA_UDMA6, 1189 .port_ops = &piix_sata_ops, 1190 }, 1191 1192 [ich8_sata] = 1193 { 1194 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1195 .pio_mask = ATA_PIO4, 1196 .mwdma_mask = ATA_MWDMA2, 1197 .udma_mask = ATA_UDMA6, 1198 .port_ops = &piix_sata_ops, 1199 }, 1200 1201 [ich8_2port_sata] = 1202 { 1203 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1204 .pio_mask = ATA_PIO4, 1205 .mwdma_mask = ATA_MWDMA2, 1206 .udma_mask = ATA_UDMA6, 1207 .port_ops = &piix_sata_ops, 1208 }, 1209 1210 [tolapai_sata] = 1211 { 1212 .flags = PIIX_SATA_FLAGS, 1213 .pio_mask = ATA_PIO4, 1214 .mwdma_mask = ATA_MWDMA2, 1215 .udma_mask = ATA_UDMA6, 1216 .port_ops = &piix_sata_ops, 1217 }, 1218 1219 [ich8m_apple_sata] = 1220 { 1221 .flags = PIIX_SATA_FLAGS, 1222 .pio_mask = ATA_PIO4, 1223 .mwdma_mask = ATA_MWDMA2, 1224 .udma_mask = ATA_UDMA6, 1225 .port_ops = &piix_sata_ops, 1226 }, 1227 1228 [piix_pata_vmw] = 1229 { 1230 .flags = PIIX_PATA_FLAGS, 1231 .pio_mask = ATA_PIO4, 1232 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1233 .udma_mask = ATA_UDMA2, 1234 .port_ops = &piix_vmw_ops, 1235 }, 1236 1237 /* 1238 * some Sandybridge chipsets have broken 32 mode up to now, 1239 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592 1240 */ 1241 [ich8_sata_snb] = 1242 { 1243 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1244 .pio_mask = ATA_PIO4, 1245 .mwdma_mask = ATA_MWDMA2, 1246 .udma_mask = ATA_UDMA6, 1247 .port_ops = &piix_sata_ops, 1248 }, 1249 1250 [ich8_2port_sata_snb] = 1251 { 1252 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR 1253 | PIIX_FLAG_PIO16, 1254 .pio_mask = ATA_PIO4, 1255 .mwdma_mask = ATA_MWDMA2, 1256 .udma_mask = ATA_UDMA6, 1257 .port_ops = &piix_sata_ops, 1258 }, 1259 1260 [ich8_2port_sata_byt] = 1261 { 1262 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1263 .pio_mask = ATA_PIO4, 1264 .mwdma_mask = ATA_MWDMA2, 1265 .udma_mask = ATA_UDMA6, 1266 .port_ops = &piix_sata_ops, 1267 }, 1268 1269}; 1270 1271#define AHCI_PCI_BAR 5 1272#define AHCI_GLOBAL_CTL 0x04 1273#define AHCI_ENABLE (1 << 31) 1274static int piix_disable_ahci(struct pci_dev *pdev) 1275{ 1276 void __iomem *mmio; 1277 u32 tmp; 1278 int rc = 0; 1279 1280 /* BUG: pci_enable_device has not yet been called. This 1281 * works because this device is usually set up by BIOS. 1282 */ 1283 1284 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1285 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1286 return 0; 1287 1288 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1289 if (!mmio) 1290 return -ENOMEM; 1291 1292 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1293 if (tmp & AHCI_ENABLE) { 1294 tmp &= ~AHCI_ENABLE; 1295 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1296 1297 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1298 if (tmp & AHCI_ENABLE) 1299 rc = -EIO; 1300 } 1301 1302 pci_iounmap(pdev, mmio); 1303 return rc; 1304} 1305 1306/** 1307 * piix_check_450nx_errata - Check for problem 450NX setup 1308 * @ata_dev: the PCI device to check 1309 * 1310 * Check for the present of 450NX errata #19 and errata #25. If 1311 * they are found return an error code so we can turn off DMA 1312 */ 1313 1314static int piix_check_450nx_errata(struct pci_dev *ata_dev) 1315{ 1316 struct pci_dev *pdev = NULL; 1317 u16 cfg; 1318 int no_piix_dma = 0; 1319 1320 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1321 /* Look for 450NX PXB. Check for problem configurations 1322 A PCI quirk checks bit 6 already */ 1323 pci_read_config_word(pdev, 0x41, &cfg); 1324 /* Only on the original revision: IDE DMA can hang */ 1325 if (pdev->revision == 0x00) 1326 no_piix_dma = 1; 1327 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1328 else if (cfg & (1<<14) && pdev->revision < 5) 1329 no_piix_dma = 2; 1330 } 1331 if (no_piix_dma) 1332 dev_warn(&ata_dev->dev, 1333 "450NX errata present, disabling IDE DMA%s\n", 1334 no_piix_dma == 2 ? " - a BIOS update may resolve this" 1335 : ""); 1336 1337 return no_piix_dma; 1338} 1339 1340static void piix_init_pcs(struct ata_host *host, 1341 const struct piix_map_db *map_db) 1342{ 1343 struct pci_dev *pdev = to_pci_dev(host->dev); 1344 u16 pcs, new_pcs; 1345 1346 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1347 1348 new_pcs = pcs | map_db->port_enable; 1349 1350 if (new_pcs != pcs) { 1351 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1352 msleep(150); 1353 } 1354} 1355 1356static const int *piix_init_sata_map(struct pci_dev *pdev, 1357 struct ata_port_info *pinfo, 1358 const struct piix_map_db *map_db) 1359{ 1360 const int *map; 1361 int i, invalid_map = 0; 1362 u8 map_value; 1363 char buf[32]; 1364 char *p = buf, *end = buf + sizeof(buf); 1365 1366 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1367 1368 map = map_db->map[map_value & map_db->mask]; 1369 1370 for (i = 0; i < 4; i++) { 1371 switch (map[i]) { 1372 case RV: 1373 invalid_map = 1; 1374 p += scnprintf(p, end - p, " XX"); 1375 break; 1376 1377 case NA: 1378 p += scnprintf(p, end - p, " --"); 1379 break; 1380 1381 case IDE: 1382 WARN_ON((i & 1) || map[i + 1] != IDE); 1383 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1384 i++; 1385 p += scnprintf(p, end - p, " IDE IDE"); 1386 break; 1387 1388 default: 1389 p += scnprintf(p, end - p, " P%d", map[i]); 1390 if (i & 1) 1391 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1392 break; 1393 } 1394 } 1395 dev_info(&pdev->dev, "MAP [%s ]\n", buf); 1396 1397 if (invalid_map) 1398 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); 1399 1400 return map; 1401} 1402 1403static bool piix_no_sidpr(struct ata_host *host) 1404{ 1405 struct pci_dev *pdev = to_pci_dev(host->dev); 1406 1407 /* 1408 * Samsung DB-P70 only has three ATA ports exposed and 1409 * curiously the unconnected first port reports link online 1410 * while not responding to SRST protocol causing excessive 1411 * detection delay. 1412 * 1413 * Unfortunately, the system doesn't carry enough DMI 1414 * information to identify the machine but does have subsystem 1415 * vendor and device set. As it's unclear whether the 1416 * subsystem vendor/device is used only for this specific 1417 * board, the port can't be disabled solely with the 1418 * information; however, turning off SIDPR access works around 1419 * the problem. Turn it off. 1420 * 1421 * This problem is reported in bnc#441240. 1422 * 1423 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1424 */ 1425 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1426 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1427 pdev->subsystem_device == 0xb049) { 1428 dev_warn(host->dev, 1429 "Samsung DB-P70 detected, disabling SIDPR\n"); 1430 return true; 1431 } 1432 1433 return false; 1434} 1435 1436static int piix_init_sidpr(struct ata_host *host) 1437{ 1438 struct pci_dev *pdev = to_pci_dev(host->dev); 1439 struct piix_host_priv *hpriv = host->private_data; 1440 struct ata_link *link0 = &host->ports[0]->link; 1441 u32 scontrol; 1442 int i, rc; 1443 1444 /* check for availability */ 1445 for (i = 0; i < 4; i++) 1446 if (hpriv->map[i] == IDE) 1447 return 0; 1448 1449 /* is it blacklisted? */ 1450 if (piix_no_sidpr(host)) 1451 return 0; 1452 1453 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1454 return 0; 1455 1456 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1457 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1458 return 0; 1459 1460 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1461 return 0; 1462 1463 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1464 1465 /* SCR access via SIDPR doesn't work on some configurations. 1466 * Give it a test drive by inhibiting power save modes which 1467 * we'll do anyway. 1468 */ 1469 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1470 1471 /* if IPM is already 3, SCR access is probably working. Don't 1472 * un-inhibit power save modes as BIOS might have inhibited 1473 * them for a reason. 1474 */ 1475 if ((scontrol & 0xf00) != 0x300) { 1476 scontrol |= 0x300; 1477 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1478 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1479 1480 if ((scontrol & 0xf00) != 0x300) { 1481 dev_info(host->dev, 1482 "SCR access via SIDPR is available but doesn't work\n"); 1483 return 0; 1484 } 1485 } 1486 1487 /* okay, SCRs available, set ops and ask libata for slave_link */ 1488 for (i = 0; i < 2; i++) { 1489 struct ata_port *ap = host->ports[i]; 1490 1491 ap->ops = &piix_sidpr_sata_ops; 1492 1493 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1494 rc = ata_slave_link_init(ap); 1495 if (rc) 1496 return rc; 1497 } 1498 } 1499 1500 return 0; 1501} 1502 1503static void piix_iocfg_bit18_quirk(struct ata_host *host) 1504{ 1505 static const struct dmi_system_id sysids[] = { 1506 { 1507 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1508 * isn't used to boot the system which 1509 * disables the channel. 1510 */ 1511 .ident = "M570U", 1512 .matches = { 1513 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1514 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1515 }, 1516 }, 1517 1518 { } /* terminate list */ 1519 }; 1520 struct pci_dev *pdev = to_pci_dev(host->dev); 1521 struct piix_host_priv *hpriv = host->private_data; 1522 1523 if (!dmi_check_system(sysids)) 1524 return; 1525 1526 /* The datasheet says that bit 18 is NOOP but certain systems 1527 * seem to use it to disable a channel. Clear the bit on the 1528 * affected systems. 1529 */ 1530 if (hpriv->saved_iocfg & (1 << 18)) { 1531 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); 1532 pci_write_config_dword(pdev, PIIX_IOCFG, 1533 hpriv->saved_iocfg & ~(1 << 18)); 1534 } 1535} 1536 1537static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1538{ 1539 static const struct dmi_system_id broken_systems[] = { 1540 { 1541 .ident = "HP Compaq 2510p", 1542 .matches = { 1543 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1544 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1545 }, 1546 /* PCI slot number of the controller */ 1547 .driver_data = (void *)0x1FUL, 1548 }, 1549 { 1550 .ident = "HP Compaq nc6000", 1551 .matches = { 1552 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1553 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1554 }, 1555 /* PCI slot number of the controller */ 1556 .driver_data = (void *)0x1FUL, 1557 }, 1558 1559 { } /* terminate list */ 1560 }; 1561 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1562 1563 if (dmi) { 1564 unsigned long slot = (unsigned long)dmi->driver_data; 1565 /* apply the quirk only to on-board controllers */ 1566 return slot == PCI_SLOT(pdev->devfn); 1567 } 1568 1569 return false; 1570} 1571 1572static int prefer_ms_hyperv = 1; 1573module_param(prefer_ms_hyperv, int, 0); 1574MODULE_PARM_DESC(prefer_ms_hyperv, 1575 "Prefer Hyper-V paravirtualization drivers instead of ATA, " 1576 "0 - Use ATA drivers, " 1577 "1 (Default) - Use the paravirtualization drivers."); 1578 1579static void piix_ignore_devices_quirk(struct ata_host *host) 1580{ 1581#if IS_ENABLED(CONFIG_HYPERV_STORAGE) 1582 static const struct dmi_system_id ignore_hyperv[] = { 1583 { 1584 /* On Hyper-V hypervisors the disks are exposed on 1585 * both the emulated SATA controller and on the 1586 * paravirtualised drivers. The CD/DVD devices 1587 * are only exposed on the emulated controller. 1588 * Request we ignore ATA devices on this host. 1589 */ 1590 .ident = "Hyper-V Virtual Machine", 1591 .matches = { 1592 DMI_MATCH(DMI_SYS_VENDOR, 1593 "Microsoft Corporation"), 1594 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1595 }, 1596 }, 1597 { } /* terminate list */ 1598 }; 1599 static const struct dmi_system_id allow_virtual_pc[] = { 1600 { 1601 /* In MS Virtual PC guests the DMI ident is nearly 1602 * identical to a Hyper-V guest. One difference is the 1603 * product version which is used here to identify 1604 * a Virtual PC guest. This entry allows ata_piix to 1605 * drive the emulated hardware. 1606 */ 1607 .ident = "MS Virtual PC 2007", 1608 .matches = { 1609 DMI_MATCH(DMI_SYS_VENDOR, 1610 "Microsoft Corporation"), 1611 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1612 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"), 1613 }, 1614 }, 1615 { } /* terminate list */ 1616 }; 1617 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv); 1618 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc); 1619 1620 if (ignore && !allow && prefer_ms_hyperv) { 1621 host->flags |= ATA_HOST_IGNORE_ATA; 1622 dev_info(host->dev, "%s detected, ATA device ignore set\n", 1623 ignore->ident); 1624 } 1625#endif 1626} 1627 1628/** 1629 * piix_init_one - Register PIIX ATA PCI device with kernel services 1630 * @pdev: PCI device to register 1631 * @ent: Entry in piix_pci_tbl matching with @pdev 1632 * 1633 * Called from kernel PCI layer. We probe for combined mode (sigh), 1634 * and then hand over control to libata, for it to do the rest. 1635 * 1636 * LOCKING: 1637 * Inherited from PCI layer (may sleep). 1638 * 1639 * RETURNS: 1640 * Zero on success, or -ERRNO value. 1641 */ 1642 1643static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1644{ 1645 struct device *dev = &pdev->dev; 1646 struct ata_port_info port_info[2]; 1647 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1648 const struct scsi_host_template *sht = &piix_sht; 1649 unsigned long port_flags; 1650 struct ata_host *host; 1651 struct piix_host_priv *hpriv; 1652 int rc; 1653 1654 ata_print_version_once(&pdev->dev, DRV_VERSION); 1655 1656 /* no hotplugging support for later devices (FIXME) */ 1657 if (!in_module_init && ent->driver_data >= ich5_sata) 1658 return -ENODEV; 1659 1660 if (piix_broken_system_poweroff(pdev)) { 1661 piix_port_info[ent->driver_data].flags |= 1662 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1663 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1664 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1665 "on poweroff and hibernation\n"); 1666 } 1667 1668 port_info[0] = piix_port_info[ent->driver_data]; 1669 port_info[1] = piix_port_info[ent->driver_data]; 1670 1671 port_flags = port_info[0].flags; 1672 1673 /* enable device and prepare host */ 1674 rc = pcim_enable_device(pdev); 1675 if (rc) 1676 return rc; 1677 1678 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1679 if (!hpriv) 1680 return -ENOMEM; 1681 1682 /* Save IOCFG, this will be used for cable detection, quirk 1683 * detection and restoration on detach. This is necessary 1684 * because some ACPI implementations mess up cable related 1685 * bits on _STM. Reported on kernel bz#11879. 1686 */ 1687 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1688 1689 /* ICH6R may be driven by either ata_piix or ahci driver 1690 * regardless of BIOS configuration. Make sure AHCI mode is 1691 * off. 1692 */ 1693 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1694 rc = piix_disable_ahci(pdev); 1695 if (rc) 1696 return rc; 1697 } 1698 1699 /* SATA map init can change port_info, do it before prepping host */ 1700 if (port_flags & ATA_FLAG_SATA) 1701 hpriv->map = piix_init_sata_map(pdev, port_info, 1702 piix_map_db_table[ent->driver_data]); 1703 1704 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 1705 if (rc) 1706 return rc; 1707 host->private_data = hpriv; 1708 1709 /* initialize controller */ 1710 if (port_flags & ATA_FLAG_SATA) { 1711 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1712 rc = piix_init_sidpr(host); 1713 if (rc) 1714 return rc; 1715 if (host->ports[0]->ops == &piix_sidpr_sata_ops) 1716 sht = &piix_sidpr_sht; 1717 } 1718 1719 /* apply IOCFG bit18 quirk */ 1720 piix_iocfg_bit18_quirk(host); 1721 1722 /* On ICH5, some BIOSen disable the interrupt using the 1723 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1724 * On ICH6, this bit has the same effect, but only when 1725 * MSI is disabled (and it is disabled, as we don't use 1726 * message-signalled interrupts currently). 1727 */ 1728 if (port_flags & PIIX_FLAG_CHECKINTR) 1729 pci_intx(pdev, 1); 1730 1731 if (piix_check_450nx_errata(pdev)) { 1732 /* This writes into the master table but it does not 1733 really matter for this errata as we will apply it to 1734 all the PIIX devices on the board */ 1735 host->ports[0]->mwdma_mask = 0; 1736 host->ports[0]->udma_mask = 0; 1737 host->ports[1]->mwdma_mask = 0; 1738 host->ports[1]->udma_mask = 0; 1739 } 1740 host->flags |= ATA_HOST_PARALLEL_SCAN; 1741 1742 /* Allow hosts to specify device types to ignore when scanning. */ 1743 piix_ignore_devices_quirk(host); 1744 1745 pci_set_master(pdev); 1746 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); 1747} 1748 1749static void piix_remove_one(struct pci_dev *pdev) 1750{ 1751 struct ata_host *host = pci_get_drvdata(pdev); 1752 struct piix_host_priv *hpriv = host->private_data; 1753 1754 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1755 1756 ata_pci_remove_one(pdev); 1757} 1758 1759static struct pci_driver piix_pci_driver = { 1760 .name = DRV_NAME, 1761 .id_table = piix_pci_tbl, 1762 .probe = piix_init_one, 1763 .remove = piix_remove_one, 1764#ifdef CONFIG_PM_SLEEP 1765 .suspend = piix_pci_device_suspend, 1766 .resume = piix_pci_device_resume, 1767#endif 1768}; 1769 1770static int __init piix_init(void) 1771{ 1772 int rc; 1773 1774 rc = pci_register_driver(&piix_pci_driver); 1775 if (rc) 1776 return rc; 1777 1778 in_module_init = 0; 1779 1780 return 0; 1781} 1782 1783static void __exit piix_exit(void) 1784{ 1785 pci_unregister_driver(&piix_pci_driver); 1786} 1787 1788module_init(piix_init); 1789module_exit(piix_exit); 1790