1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DaVinci DM816 AHCI SATA platform driver
4 *
5 * Copyright (C) 2017 BayLibre SAS
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/device.h>
11#include <linux/pm.h>
12#include <linux/platform_device.h>
13#include <linux/libata.h>
14#include <linux/ahci_platform.h>
15
16#include "ahci.h"
17
18#define AHCI_DM816_DRV_NAME		"ahci-dm816"
19
20#define AHCI_DM816_PHY_ENPLL(x)		((x) << 0)
21#define AHCI_DM816_PHY_MPY(x)		((x) << 1)
22#define AHCI_DM816_PHY_LOS(x)		((x) << 12)
23#define AHCI_DM816_PHY_RXCDR(x)		((x) << 13)
24#define AHCI_DM816_PHY_RXEQ(x)		((x) << 16)
25#define AHCI_DM816_PHY_TXSWING(x)	((x) << 23)
26
27#define AHCI_DM816_P0PHYCR_REG		0x178
28#define AHCI_DM816_P1PHYCR_REG		0x1f8
29
30#define AHCI_DM816_PLL_OUT		1500000000LU
31
32static const unsigned long pll_mpy_table[] = {
33	  400,  500,  600,  800,  825, 1000, 1200,
34	 1250, 1500, 1600, 1650, 2000, 2200, 2500
35};
36
37static int ahci_dm816_get_mpy_bits(unsigned long refclk_rate)
38{
39	unsigned long pll_multiplier;
40	int i;
41
42	/*
43	 * We need to determine the value of the multiplier (MPY) bits.
44	 * In order to include the 8.25 multiplier we need to first divide
45	 * the refclk rate by 100.
46	 */
47	pll_multiplier = AHCI_DM816_PLL_OUT / (refclk_rate / 100);
48
49	for (i = 0; i < ARRAY_SIZE(pll_mpy_table); i++) {
50		if (pll_mpy_table[i] == pll_multiplier)
51			return i;
52	}
53
54	/*
55	 * We should have divided evenly - if not, return an invalid
56	 * value.
57	 */
58	return -1;
59}
60
61static int ahci_dm816_phy_init(struct ahci_host_priv *hpriv, struct device *dev)
62{
63	unsigned long refclk_rate;
64	int mpy;
65	u32 val;
66
67	/*
68	 * We should have been supplied two clocks: the functional and
69	 * keep-alive clock and the external reference clock. We need the
70	 * rate of the latter to calculate the correct value of MPY bits.
71	 */
72	if (hpriv->n_clks < 2) {
73		dev_err(dev, "reference clock not supplied\n");
74		return -EINVAL;
75	}
76
77	refclk_rate = clk_get_rate(hpriv->clks[1].clk);
78	if ((refclk_rate % 100) != 0) {
79		dev_err(dev, "reference clock rate must be divisible by 100\n");
80		return -EINVAL;
81	}
82
83	mpy = ahci_dm816_get_mpy_bits(refclk_rate);
84	if (mpy < 0) {
85		dev_err(dev, "can't calculate the MPY bits value\n");
86		return -EINVAL;
87	}
88
89	/* Enable the PHY and configure the first HBA port. */
90	val = AHCI_DM816_PHY_MPY(mpy) | AHCI_DM816_PHY_LOS(1) |
91	      AHCI_DM816_PHY_RXCDR(4) | AHCI_DM816_PHY_RXEQ(1) |
92	      AHCI_DM816_PHY_TXSWING(3) | AHCI_DM816_PHY_ENPLL(1);
93	writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG);
94
95	/* Configure the second HBA port. */
96	val = AHCI_DM816_PHY_LOS(1) | AHCI_DM816_PHY_RXCDR(4) |
97	      AHCI_DM816_PHY_RXEQ(1) | AHCI_DM816_PHY_TXSWING(3);
98	writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG);
99
100	return 0;
101}
102
103static int ahci_dm816_softreset(struct ata_link *link,
104				unsigned int *class, unsigned long deadline)
105{
106	int pmp, ret;
107
108	pmp = sata_srst_pmp(link);
109
110	/*
111	 * There's an issue with the SATA controller on DM816 SoC: if we
112	 * enable Port Multiplier support, but the drive is connected directly
113	 * to the board, it can't be detected. As a workaround: if PMP is
114	 * enabled, we first call ahci_do_softreset() and pass it the result of
115	 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
116	 */
117	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
118	if (pmp && ret == -EBUSY)
119		return ahci_do_softreset(link, class, 0,
120					 deadline, ahci_check_ready);
121
122	return ret;
123}
124
125static struct ata_port_operations ahci_dm816_port_ops = {
126	.inherits = &ahci_platform_ops,
127	.softreset = ahci_dm816_softreset,
128};
129
130static const struct ata_port_info ahci_dm816_port_info = {
131	.flags		= AHCI_FLAG_COMMON,
132	.pio_mask	= ATA_PIO4,
133	.udma_mask	= ATA_UDMA6,
134	.port_ops	= &ahci_dm816_port_ops,
135};
136
137static const struct scsi_host_template ahci_dm816_platform_sht = {
138	AHCI_SHT(AHCI_DM816_DRV_NAME),
139};
140
141static int ahci_dm816_probe(struct platform_device *pdev)
142{
143	struct device *dev = &pdev->dev;
144	struct ahci_host_priv *hpriv;
145	int rc;
146
147	hpriv = ahci_platform_get_resources(pdev, 0);
148	if (IS_ERR(hpriv))
149		return PTR_ERR(hpriv);
150
151	rc = ahci_platform_enable_resources(hpriv);
152	if (rc)
153		return rc;
154
155	rc = ahci_dm816_phy_init(hpriv, dev);
156	if (rc)
157		goto disable_resources;
158
159	rc = ahci_platform_init_host(pdev, hpriv,
160				     &ahci_dm816_port_info,
161				     &ahci_dm816_platform_sht);
162	if (rc)
163		goto disable_resources;
164
165	return 0;
166
167disable_resources:
168	ahci_platform_disable_resources(hpriv);
169
170	return rc;
171}
172
173static SIMPLE_DEV_PM_OPS(ahci_dm816_pm_ops,
174			 ahci_platform_suspend,
175			 ahci_platform_resume);
176
177static const struct of_device_id ahci_dm816_of_match[] = {
178	{ .compatible = "ti,dm816-ahci", },
179	{ /* sentinel */ }
180};
181MODULE_DEVICE_TABLE(of, ahci_dm816_of_match);
182
183static struct platform_driver ahci_dm816_driver = {
184	.probe = ahci_dm816_probe,
185	.remove_new = ata_platform_remove_one,
186	.driver = {
187		.name = AHCI_DM816_DRV_NAME,
188		.of_match_table = ahci_dm816_of_match,
189		.pm = &ahci_dm816_pm_ops,
190	},
191};
192module_platform_driver(ahci_dm816_driver);
193
194MODULE_DESCRIPTION("DaVinci DM816 AHCI SATA platform driver");
195MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
196MODULE_LICENSE("GPL");
197