1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA_QM_0_REGS_H_ 14#define ASIC_REG_DMA_QM_0_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA_QM_0 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmDMA_QM_0_GLBL_CFG0 0x400000 23 24#define mmDMA_QM_0_GLBL_CFG1 0x400004 25 26#define mmDMA_QM_0_GLBL_PROT 0x400008 27 28#define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C 29 30#define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010 31 32#define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014 33 34#define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018 35 36#define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C 37 38#define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020 39 40#define mmDMA_QM_0_GLBL_STS0 0x400024 41 42#define mmDMA_QM_0_GLBL_STS1 0x400028 43 44#define mmDMA_QM_0_PQ_BASE_LO 0x400060 45 46#define mmDMA_QM_0_PQ_BASE_HI 0x400064 47 48#define mmDMA_QM_0_PQ_SIZE 0x400068 49 50#define mmDMA_QM_0_PQ_PI 0x40006C 51 52#define mmDMA_QM_0_PQ_CI 0x400070 53 54#define mmDMA_QM_0_PQ_CFG0 0x400074 55 56#define mmDMA_QM_0_PQ_CFG1 0x400078 57 58#define mmDMA_QM_0_PQ_ARUSER 0x40007C 59 60#define mmDMA_QM_0_PQ_PUSH0 0x400080 61 62#define mmDMA_QM_0_PQ_PUSH1 0x400084 63 64#define mmDMA_QM_0_PQ_PUSH2 0x400088 65 66#define mmDMA_QM_0_PQ_PUSH3 0x40008C 67 68#define mmDMA_QM_0_PQ_STS0 0x400090 69 70#define mmDMA_QM_0_PQ_STS1 0x400094 71 72#define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0 73 74#define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4 75 76#define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8 77 78#define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC 79 80#define mmDMA_QM_0_CQ_CFG0 0x4000B0 81 82#define mmDMA_QM_0_CQ_CFG1 0x4000B4 83 84#define mmDMA_QM_0_CQ_ARUSER 0x4000B8 85 86#define mmDMA_QM_0_CQ_PTR_LO 0x4000C0 87 88#define mmDMA_QM_0_CQ_PTR_HI 0x4000C4 89 90#define mmDMA_QM_0_CQ_TSIZE 0x4000C8 91 92#define mmDMA_QM_0_CQ_CTL 0x4000CC 93 94#define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4 95 96#define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8 97 98#define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC 99 100#define mmDMA_QM_0_CQ_CTL_STS 0x4000E0 101 102#define mmDMA_QM_0_CQ_STS0 0x4000E4 103 104#define mmDMA_QM_0_CQ_STS1 0x4000E8 105 106#define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0 107 108#define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4 109 110#define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8 111 112#define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC 113 114#define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108 115 116#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120 117 118#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124 119 120#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128 121 122#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C 123 124#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130 125 126#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134 127 128#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138 129 130#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C 131 132#define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140 133 134#define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144 135 136#define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148 137 138#define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C 139 140#define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150 141 142#define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154 143 144#define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158 145 146#define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C 147 148#define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160 149 150#define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164 151 152#define mmDMA_QM_0_CP_FENCE0_CNT 0x400168 153 154#define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C 155 156#define mmDMA_QM_0_CP_FENCE2_CNT 0x400170 157 158#define mmDMA_QM_0_CP_FENCE3_CNT 0x400174 159 160#define mmDMA_QM_0_CP_STS 0x400178 161 162#define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C 163 164#define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180 165 166#define mmDMA_QM_0_CP_BARRIER_CFG 0x400184 167 168#define mmDMA_QM_0_CP_DBG_0 0x400188 169 170#define mmDMA_QM_0_PQ_BUF_ADDR 0x400300 171 172#define mmDMA_QM_0_PQ_BUF_RDATA 0x400304 173 174#define mmDMA_QM_0_CQ_BUF_ADDR 0x400308 175 176#define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C 177 178#endif /* ASIC_REG_DMA_QM_0_REGS_H_ */ 179