1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2020 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 **       DO NOT EDIT BELOW        **
11 ************************************/
12
13#ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_
14#define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_
15
16/*
17 *****************************************
18 *   DCORE0_EDMA0_CORE
19 *   (Prototype: DMA_CORE)
20 *****************************************
21 */
22
23#define mmDCORE0_EDMA0_CORE_CFG_0 0x41CB000
24
25#define mmDCORE0_EDMA0_CORE_CFG_1 0x41CB004
26
27#define mmDCORE0_EDMA0_CORE_PROT 0x41CB008
28
29#define mmDCORE0_EDMA0_CORE_CKG 0x41CB00C
30
31#define mmDCORE0_EDMA0_CORE_RD_GLBL 0x41CB07C
32
33#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x41CB080
34
35#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE 0x41CB084
36
37#define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE 0x41CB088
38
39#define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS 0x41CB090
40
41#define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x41CB094
42
43#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x41CB0C0
44
45#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE 0x41CB0C4
46
47#define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE 0x41CB0C8
48
49#define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS 0x41CB0D0
50
51#define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x41CB0D4
52
53#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x41CB100
54
55#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID 0x41CB104
56
57#define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE 0x41CB108
58
59#define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS 0x41CB10C
60
61#define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x41CB110
62
63#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x41CB140
64
65#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID 0x41CB144
66
67#define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE 0x41CB148
68
69#define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS 0x41CB14C
70
71#define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x41CB150
72
73#define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x41CB180
74
75#define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER 0x41CB184
76
77#define mmDCORE0_EDMA0_CORE_ERR_CFG 0x41CB300
78
79#define mmDCORE0_EDMA0_CORE_ERR_CAUSE 0x41CB304
80
81#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO 0x41CB308
82
83#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI 0x41CB30C
84
85#define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA 0x41CB310
86
87#define mmDCORE0_EDMA0_CORE_STS0 0x41CB380
88
89#define mmDCORE0_EDMA0_CORE_STS1 0x41CB384
90
91#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL 0x41CB400
92
93#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE 0x41CB404
94
95#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO 0x41CB408
96
97#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI 0x41CB40C
98
99#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID 0x41CB410
100
101#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x41CB414
102
103#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x41CB418
104
105#define mmDCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR 0x41CB41C
106
107#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SEL 0x41CB420
108
109#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SIZE 0x41CB424
110
111#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO 0x41CB428
112
113#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI 0x41CB42C
114
115#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_ID 0x41CB430
116
117#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x41CB434
118
119#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x41CB438
120
121#define mmDCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR 0x41CB43C
122
123#define mmDCORE0_EDMA0_CORE_PWRLP_CFG 0x41CB700
124
125#define mmDCORE0_EDMA0_CORE_PWRLP_STS 0x41CB704
126
127#define mmDCORE0_EDMA0_CORE_DBG_DESC_CNT 0x41CB710
128
129#define mmDCORE0_EDMA0_CORE_DBG_STS 0x41CB714
130
131#define mmDCORE0_EDMA0_CORE_DBG_BUF_STS 0x41CB718
132
133#define mmDCORE0_EDMA0_CORE_DBG_RD_DESC_ID 0x41CB720
134
135#define mmDCORE0_EDMA0_CORE_DBG_WR_DESC_ID 0x41CB724
136
137#define mmDCORE0_EDMA0_CORE_APB_DMA_LBW_BASE 0x41CB728
138
139#define mmDCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x41CB72C
140
141#define mmDCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG 0x41CB730
142
143#define mmDCORE0_EDMA0_CORE_DBG_APB_ENABLER 0x41CBE1C
144
145#define mmDCORE0_EDMA0_CORE_L2H_CMPR_LO 0x41CBE20
146
147#define mmDCORE0_EDMA0_CORE_L2H_CMPR_HI 0x41CBE24
148
149#define mmDCORE0_EDMA0_CORE_L2H_MASK_LO 0x41CBE28
150
151#define mmDCORE0_EDMA0_CORE_L2H_MASK_HI 0x41CBE2C
152
153#define mmDCORE0_EDMA0_CORE_IDLE_IND_MASK 0x41CBE30
154
155#define mmDCORE0_EDMA0_CORE_APB_ENABLER 0x41CBE34
156
157#endif /* ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ */
158