1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC1_QM_REGS_H_ 14#define ASIC_REG_TPC1_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC1_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmTPC1_QM_GLBL_CFG0 0xE48000 23 24#define mmTPC1_QM_GLBL_CFG1 0xE48004 25 26#define mmTPC1_QM_GLBL_PROT 0xE48008 27 28#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C 29 30#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010 31 32#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014 33 34#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018 35 36#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C 37 38#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020 39 40#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024 41 42#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028 43 44#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C 45 46#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030 47 48#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034 49 50#define mmTPC1_QM_GLBL_STS0 0xE48038 51 52#define mmTPC1_QM_GLBL_STS1_0 0xE48040 53 54#define mmTPC1_QM_GLBL_STS1_1 0xE48044 55 56#define mmTPC1_QM_GLBL_STS1_2 0xE48048 57 58#define mmTPC1_QM_GLBL_STS1_3 0xE4804C 59 60#define mmTPC1_QM_GLBL_STS1_4 0xE48050 61 62#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054 63 64#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058 65 66#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C 67 68#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060 69 70#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068 71 72#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070 73 74#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074 75 76#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078 77 78#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C 79 80#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080 81 82#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084 83 84#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088 85 86#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C 87 88#define mmTPC1_QM_PQ_SIZE_0 0xE48090 89 90#define mmTPC1_QM_PQ_SIZE_1 0xE48094 91 92#define mmTPC1_QM_PQ_SIZE_2 0xE48098 93 94#define mmTPC1_QM_PQ_SIZE_3 0xE4809C 95 96#define mmTPC1_QM_PQ_PI_0 0xE480A0 97 98#define mmTPC1_QM_PQ_PI_1 0xE480A4 99 100#define mmTPC1_QM_PQ_PI_2 0xE480A8 101 102#define mmTPC1_QM_PQ_PI_3 0xE480AC 103 104#define mmTPC1_QM_PQ_CI_0 0xE480B0 105 106#define mmTPC1_QM_PQ_CI_1 0xE480B4 107 108#define mmTPC1_QM_PQ_CI_2 0xE480B8 109 110#define mmTPC1_QM_PQ_CI_3 0xE480BC 111 112#define mmTPC1_QM_PQ_CFG0_0 0xE480C0 113 114#define mmTPC1_QM_PQ_CFG0_1 0xE480C4 115 116#define mmTPC1_QM_PQ_CFG0_2 0xE480C8 117 118#define mmTPC1_QM_PQ_CFG0_3 0xE480CC 119 120#define mmTPC1_QM_PQ_CFG1_0 0xE480D0 121 122#define mmTPC1_QM_PQ_CFG1_1 0xE480D4 123 124#define mmTPC1_QM_PQ_CFG1_2 0xE480D8 125 126#define mmTPC1_QM_PQ_CFG1_3 0xE480DC 127 128#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0 129 130#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4 131 132#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8 133 134#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC 135 136#define mmTPC1_QM_PQ_STS0_0 0xE480F0 137 138#define mmTPC1_QM_PQ_STS0_1 0xE480F4 139 140#define mmTPC1_QM_PQ_STS0_2 0xE480F8 141 142#define mmTPC1_QM_PQ_STS0_3 0xE480FC 143 144#define mmTPC1_QM_PQ_STS1_0 0xE48100 145 146#define mmTPC1_QM_PQ_STS1_1 0xE48104 147 148#define mmTPC1_QM_PQ_STS1_2 0xE48108 149 150#define mmTPC1_QM_PQ_STS1_3 0xE4810C 151 152#define mmTPC1_QM_CQ_CFG0_0 0xE48110 153 154#define mmTPC1_QM_CQ_CFG0_1 0xE48114 155 156#define mmTPC1_QM_CQ_CFG0_2 0xE48118 157 158#define mmTPC1_QM_CQ_CFG0_3 0xE4811C 159 160#define mmTPC1_QM_CQ_CFG0_4 0xE48120 161 162#define mmTPC1_QM_CQ_CFG1_0 0xE48124 163 164#define mmTPC1_QM_CQ_CFG1_1 0xE48128 165 166#define mmTPC1_QM_CQ_CFG1_2 0xE4812C 167 168#define mmTPC1_QM_CQ_CFG1_3 0xE48130 169 170#define mmTPC1_QM_CQ_CFG1_4 0xE48134 171 172#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138 173 174#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C 175 176#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140 177 178#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144 179 180#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148 181 182#define mmTPC1_QM_CQ_STS0_0 0xE4814C 183 184#define mmTPC1_QM_CQ_STS0_1 0xE48150 185 186#define mmTPC1_QM_CQ_STS0_2 0xE48154 187 188#define mmTPC1_QM_CQ_STS0_3 0xE48158 189 190#define mmTPC1_QM_CQ_STS0_4 0xE4815C 191 192#define mmTPC1_QM_CQ_STS1_0 0xE48160 193 194#define mmTPC1_QM_CQ_STS1_1 0xE48164 195 196#define mmTPC1_QM_CQ_STS1_2 0xE48168 197 198#define mmTPC1_QM_CQ_STS1_3 0xE4816C 199 200#define mmTPC1_QM_CQ_STS1_4 0xE48170 201 202#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174 203 204#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178 205 206#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C 207 208#define mmTPC1_QM_CQ_CTL_0 0xE48180 209 210#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184 211 212#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188 213 214#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C 215 216#define mmTPC1_QM_CQ_CTL_1 0xE48190 217 218#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194 219 220#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198 221 222#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C 223 224#define mmTPC1_QM_CQ_CTL_2 0xE481A0 225 226#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4 227 228#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8 229 230#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC 231 232#define mmTPC1_QM_CQ_CTL_3 0xE481B0 233 234#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4 235 236#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8 237 238#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC 239 240#define mmTPC1_QM_CQ_CTL_4 0xE481C0 241 242#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4 243 244#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8 245 246#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC 247 248#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0 249 250#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4 251 252#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8 253 254#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC 255 256#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0 257 258#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4 259 260#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8 261 262#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC 263 264#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0 265 266#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4 267 268#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8 269 270#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC 271 272#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200 273 274#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204 275 276#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208 277 278#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C 279 280#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210 281 282#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214 283 284#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218 285 286#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C 287 288#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220 289 290#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224 291 292#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228 293 294#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C 295 296#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230 297 298#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234 299 300#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238 301 302#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C 303 304#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240 305 306#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244 307 308#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248 309 310#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C 311 312#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250 313 314#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254 315 316#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258 317 318#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C 319 320#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260 321 322#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264 323 324#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268 325 326#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C 327 328#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270 329 330#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274 331 332#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278 333 334#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C 335 336#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280 337 338#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284 339 340#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288 341 342#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C 343 344#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290 345 346#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294 347 348#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298 349 350#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C 351 352#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0 353 354#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4 355 356#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8 357 358#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC 359 360#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0 361 362#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4 363 364#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8 365 366#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC 367 368#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0 369 370#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4 371 372#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8 373 374#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC 375 376#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0 377 378#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4 379 380#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8 381 382#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0 383 384#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4 385 386#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8 387 388#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC 389 390#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0 391 392#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4 393 394#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8 395 396#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC 397 398#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300 399 400#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304 401 402#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308 403 404#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C 405 406#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310 407 408#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314 409 410#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318 411 412#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C 413 414#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320 415 416#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324 417 418#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328 419 420#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C 421 422#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330 423 424#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334 425 426#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338 427 428#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C 429 430#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340 431 432#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344 433 434#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348 435 436#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C 437 438#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350 439 440#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354 441 442#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358 443 444#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C 445 446#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360 447 448#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364 449 450#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368 451 452#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C 453 454#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370 455 456#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374 457 458#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378 459 460#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C 461 462#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380 463 464#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384 465 466#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388 467 468#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C 469 470#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390 471 472#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394 473 474#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398 475 476#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C 477 478#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0 479 480#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4 481 482#define mmTPC1_QM_CP_STS_0 0xE483A8 483 484#define mmTPC1_QM_CP_STS_1 0xE483AC 485 486#define mmTPC1_QM_CP_STS_2 0xE483B0 487 488#define mmTPC1_QM_CP_STS_3 0xE483B4 489 490#define mmTPC1_QM_CP_STS_4 0xE483B8 491 492#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC 493 494#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0 495 496#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4 497 498#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8 499 500#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC 501 502#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0 503 504#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4 505 506#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8 507 508#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC 509 510#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0 511 512#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4 513 514#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8 515 516#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC 517 518#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400 519 520#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404 521 522#define mmTPC1_QM_CP_DBG_0_0 0xE48408 523 524#define mmTPC1_QM_CP_DBG_0_1 0xE4840C 525 526#define mmTPC1_QM_CP_DBG_0_2 0xE48410 527 528#define mmTPC1_QM_CP_DBG_0_3 0xE48414 529 530#define mmTPC1_QM_CP_DBG_0_4 0xE48418 531 532#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C 533 534#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420 535 536#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424 537 538#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428 539 540#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C 541 542#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430 543 544#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434 545 546#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438 547 548#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C 549 550#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440 551 552#define mmTPC1_QM_ARB_CFG_0 0xE48A00 553 554#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04 555 556#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08 557 558#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C 559 560#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10 561 562#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14 563 564#define mmTPC1_QM_ARB_CFG_1 0xE48A18 565 566#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20 567 568#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24 569 570#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28 571 572#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C 573 574#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30 575 576#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34 577 578#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38 579 580#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C 581 582#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40 583 584#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44 585 586#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48 587 588#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C 589 590#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50 591 592#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54 593 594#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58 595 596#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C 597 598#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60 599 600#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64 601 602#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68 603 604#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C 605 606#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70 607 608#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74 609 610#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78 611 612#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C 613 614#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80 615 616#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84 617 618#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88 619 620#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C 621 622#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90 623 624#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94 625 626#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98 627 628#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C 629 630#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0 631 632#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4 633 634#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8 635 636#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC 637 638#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0 639 640#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4 641 642#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8 643 644#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC 645 646#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0 647 648#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4 649 650#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8 651 652#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC 653 654#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0 655 656#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4 657 658#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8 659 660#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC 661 662#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0 663 664#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4 665 666#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8 667 668#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC 669 670#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0 671 672#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4 673 674#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8 675 676#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC 677 678#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00 679 680#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04 681 682#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08 683 684#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C 685 686#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10 687 688#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14 689 690#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18 691 692#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C 693 694#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20 695 696#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28 697 698#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C 699 700#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34 701 702#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38 703 704#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C 705 706#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44 707 708#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48 709 710#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C 711 712#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50 713 714#define mmTPC1_QM_ARB_BASE_LO 0xE48B54 715 716#define mmTPC1_QM_ARB_BASE_HI 0xE48B58 717 718#define mmTPC1_QM_ARB_STATE_STS 0xE48B80 719 720#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84 721 722#define mmTPC1_QM_ARB_MSG_STS 0xE48B88 723 724#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C 725 726#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C 727 728#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0 729 730#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8 731 732#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0 733 734#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4 735 736#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8 737 738#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC 739 740#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0 741 742#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4 743 744#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8 745 746#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC 747 748#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0 749 750#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4 751 752#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8 753 754#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC 755 756#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0 757 758#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4 759 760#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8 761 762#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC 763 764#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0 765 766#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4 767 768#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8 769 770#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC 771 772#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00 773 774#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04 775 776#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08 777 778#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C 779 780#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10 781 782#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14 783 784#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18 785 786#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C 787 788#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20 789 790#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24 791 792#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28 793 794#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C 795 796#define mmTPC1_QM_CGM_CFG 0xE48C70 797 798#define mmTPC1_QM_CGM_STS 0xE48C74 799 800#define mmTPC1_QM_CGM_CFG1 0xE48C78 801 802#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80 803 804#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84 805 806#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90 807 808#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94 809 810#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98 811 812#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C 813 814#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0 815 816#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4 817 818#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0 819 820#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4 821 822#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8 823 824#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC 825 826#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0 827 828#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4 829 830#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8 831 832#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00 833 834#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ 835