1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC0_QM_MASKS_H_ 14#define ASIC_REG_TPC0_QM_MASKS_H_ 15 16/* 17 ***************************************** 18 * TPC0_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22/* TPC0_QM_GLBL_CFG0 */ 23#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 24#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF 25#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 26#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 27#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 9 28#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 29 30/* TPC0_QM_GLBL_CFG1 */ 31#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 32#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF 33#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 34#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 35#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 36#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 37#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 38#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 39#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 40#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 41#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 42#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 43 44/* TPC0_QM_GLBL_PROT */ 45#define TPC0_QM_GLBL_PROT_PQF_SHIFT 0 46#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF 47#define TPC0_QM_GLBL_PROT_CQF_SHIFT 4 48#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F0 49#define TPC0_QM_GLBL_PROT_CP_SHIFT 9 50#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E00 51#define TPC0_QM_GLBL_PROT_ERR_SHIFT 14 52#define TPC0_QM_GLBL_PROT_ERR_MASK 0x4000 53#define TPC0_QM_GLBL_PROT_ARB_SHIFT 15 54#define TPC0_QM_GLBL_PROT_ARB_MASK 0x8000 55 56/* TPC0_QM_GLBL_ERR_CFG */ 57#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 58#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF 59#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 60#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 61#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 62#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 63#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 64#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 65#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 66#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 67#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 68#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 69#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 70#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 71 72/* TPC0_QM_GLBL_SECURE_PROPS */ 73#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 74#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF 75#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 76#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF 77#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 78#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF 79#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 80#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF 81#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 82#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF 83#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 84#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 85#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 86#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 87#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 88#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 89#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 90#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 91#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 92#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 93 94/* TPC0_QM_GLBL_NON_SECURE_PROPS */ 95#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 96#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF 97#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 98#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF 99#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 100#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF 101#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 102#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF 103#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 104#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF 105#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 106#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 107#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 108#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 109#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 110#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 111#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 112#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 113#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 114#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 115 116/* TPC0_QM_GLBL_STS0 */ 117#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 118#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF 119#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 120#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 121#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 122#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 123#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 124#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 125#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 126#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 127#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 128#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 129#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 130#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 131 132/* TPC0_QM_GLBL_STS1 */ 133#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 134#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 135#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 136#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 137#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 138#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 139#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 140#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 141#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 142#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 143#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 144#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 145#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 146#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 147#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 148#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 149#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 150#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 151#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 152#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 153#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 154#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 155#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 156#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 157#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 158#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 159#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 160#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 161#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 162#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 163 164/* TPC0_QM_GLBL_STS1_4 */ 165#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 166#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 167#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 168#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 169#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 170#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 171#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 172#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 173#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 174#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 175#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 176#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 177#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 178#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 179#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 180#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 181#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 182#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 183#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 184#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 185#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 186#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 187#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 188#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 189#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 190#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 191#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 192#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 193 194/* TPC0_QM_GLBL_MSG_EN */ 195#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 196#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 197#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 198#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 199#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 200#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 201#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 202#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 203#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 204#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 205#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 206#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 207#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 208#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 209#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 210#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 211#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 212#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 213#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 214#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 215#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 216#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 217#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 218#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 219#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 220#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 221#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 222#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 223#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 224#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 225 226/* TPC0_QM_GLBL_MSG_EN_4 */ 227#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 228#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 229#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 230#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 231#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 232#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 233#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 234#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 235#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 236#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 237#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 238#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 239#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 240#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 241#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 242#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 243#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 244#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 245#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 246#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 247#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 248#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 249#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 250#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 251#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 252#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 253#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 254#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 255 256/* TPC0_QM_PQ_BASE_LO */ 257#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 258#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF 259 260/* TPC0_QM_PQ_BASE_HI */ 261#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 262#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF 263 264/* TPC0_QM_PQ_SIZE */ 265#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 266#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF 267 268/* TPC0_QM_PQ_PI */ 269#define TPC0_QM_PQ_PI_VAL_SHIFT 0 270#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF 271 272/* TPC0_QM_PQ_CI */ 273#define TPC0_QM_PQ_CI_VAL_SHIFT 0 274#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF 275 276/* TPC0_QM_PQ_CFG0 */ 277#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 278#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 279 280/* TPC0_QM_PQ_CFG1 */ 281#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 282#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF 283#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 284#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 285 286/* TPC0_QM_PQ_ARUSER_31_11 */ 287#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 288#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF 289 290/* TPC0_QM_PQ_STS0 */ 291#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 292#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF 293#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 294#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 295 296/* TPC0_QM_PQ_STS1 */ 297#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 298#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF 299#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 300#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 301#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 302#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 303 304/* TPC0_QM_CQ_CFG0 */ 305#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 306#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 307 308/* TPC0_QM_CQ_CFG1 */ 309#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 310#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF 311#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 312#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 313 314/* TPC0_QM_CQ_ARUSER_31_11 */ 315#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 316#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF 317 318/* TPC0_QM_CQ_STS0 */ 319#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 320#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF 321#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 322#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 323 324/* TPC0_QM_CQ_STS1 */ 325#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 326#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF 327#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 328#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 329#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 330#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 331 332/* TPC0_QM_CQ_PTR_LO_0 */ 333#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 334#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF 335 336/* TPC0_QM_CQ_PTR_HI_0 */ 337#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 338#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF 339 340/* TPC0_QM_CQ_TSIZE_0 */ 341#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0 342#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF 343 344/* TPC0_QM_CQ_CTL_0 */ 345#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0 346#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF 347#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16 348#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 349 350/* TPC0_QM_CQ_PTR_LO_1 */ 351#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 352#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF 353 354/* TPC0_QM_CQ_PTR_HI_1 */ 355#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 356#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF 357 358/* TPC0_QM_CQ_TSIZE_1 */ 359#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0 360#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF 361 362/* TPC0_QM_CQ_CTL_1 */ 363#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0 364#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF 365#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16 366#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 367 368/* TPC0_QM_CQ_PTR_LO_2 */ 369#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 370#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF 371 372/* TPC0_QM_CQ_PTR_HI_2 */ 373#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 374#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF 375 376/* TPC0_QM_CQ_TSIZE_2 */ 377#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0 378#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF 379 380/* TPC0_QM_CQ_CTL_2 */ 381#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0 382#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF 383#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16 384#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 385 386/* TPC0_QM_CQ_PTR_LO_3 */ 387#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 388#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF 389 390/* TPC0_QM_CQ_PTR_HI_3 */ 391#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 392#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF 393 394/* TPC0_QM_CQ_TSIZE_3 */ 395#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0 396#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF 397 398/* TPC0_QM_CQ_CTL_3 */ 399#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0 400#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF 401#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16 402#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 403 404/* TPC0_QM_CQ_PTR_LO_4 */ 405#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 406#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF 407 408/* TPC0_QM_CQ_PTR_HI_4 */ 409#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 410#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF 411 412/* TPC0_QM_CQ_TSIZE_4 */ 413#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0 414#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF 415 416/* TPC0_QM_CQ_CTL_4 */ 417#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0 418#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF 419#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16 420#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 421 422/* TPC0_QM_CQ_PTR_LO_STS */ 423#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 424#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 425 426/* TPC0_QM_CQ_PTR_HI_STS */ 427#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 428#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 429 430/* TPC0_QM_CQ_TSIZE_STS */ 431#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 432#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 433 434/* TPC0_QM_CQ_CTL_STS */ 435#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 436#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF 437#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 438#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 439 440/* TPC0_QM_CQ_IFIFO_CNT */ 441#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 442#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 443 444/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ 445#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 446#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF 447 448/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ 449#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 450#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF 451 452/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ 453#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 454#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF 455 456/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ 457#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 458#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF 459 460/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ 461#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 462#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF 463 464/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ 465#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 466#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF 467 468/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ 469#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 470#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF 471 472/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ 473#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 474#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF 475 476/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ 477#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 478#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF 479 480/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ 481#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 482#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 483 484/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ 485#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 486#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 487 488/* TPC0_QM_CP_FENCE0_RDATA */ 489#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 490#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF 491 492/* TPC0_QM_CP_FENCE1_RDATA */ 493#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 494#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF 495 496/* TPC0_QM_CP_FENCE2_RDATA */ 497#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 498#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF 499 500/* TPC0_QM_CP_FENCE3_RDATA */ 501#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 502#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF 503 504/* TPC0_QM_CP_FENCE0_CNT */ 505#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 506#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF 507 508/* TPC0_QM_CP_FENCE1_CNT */ 509#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 510#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF 511 512/* TPC0_QM_CP_FENCE2_CNT */ 513#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 514#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF 515 516/* TPC0_QM_CP_FENCE3_CNT */ 517#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 518#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF 519 520/* TPC0_QM_CP_STS */ 521#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 522#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF 523#define TPC0_QM_CP_STS_ERDY_SHIFT 16 524#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 525#define TPC0_QM_CP_STS_RRDY_SHIFT 17 526#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 527#define TPC0_QM_CP_STS_MRDY_SHIFT 18 528#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 529#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 530#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 531#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 532#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 533#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 534#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 535 536/* TPC0_QM_CP_CURRENT_INST_LO */ 537#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 538#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF 539 540/* TPC0_QM_CP_CURRENT_INST_HI */ 541#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 542#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF 543 544/* TPC0_QM_CP_BARRIER_CFG */ 545#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 546#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF 547#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 548#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 549 550/* TPC0_QM_CP_DBG_0 */ 551#define TPC0_QM_CP_DBG_0_CS_SHIFT 0 552#define TPC0_QM_CP_DBG_0_CS_MASK 0xF 553#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 554#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 555#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 556#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 557#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 558#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 559#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7 560#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80 561 562/* TPC0_QM_CP_ARUSER_31_11 */ 563#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 564#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF 565 566/* TPC0_QM_CP_AWUSER_31_11 */ 567#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 568#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF 569 570/* TPC0_QM_ARB_CFG_0 */ 571#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0 572#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1 573#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 574#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 575#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8 576#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100 577#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12 578#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000 579#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 580#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 581 582/* TPC0_QM_ARB_CHOISE_Q_PUSH */ 583#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 584#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 585 586/* TPC0_QM_ARB_WRR_WEIGHT */ 587#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 588#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF 589 590/* TPC0_QM_ARB_CFG_1 */ 591#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0 592#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1 593 594/* TPC0_QM_ARB_MST_AVAIL_CRED */ 595#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 596#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F 597 598/* TPC0_QM_ARB_MST_CRED_INC */ 599#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 600#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF 601 602/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */ 603#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 604#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF 605 606/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ 607#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 608#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF 609 610/* TPC0_QM_ARB_MST_SLAVE_EN */ 611#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 612#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF 613 614/* TPC0_QM_ARB_MST_QUIET_PER */ 615#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 616#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF 617 618/* TPC0_QM_ARB_SLV_CHOISE_WDT */ 619#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 620#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF 621 622/* TPC0_QM_ARB_SLV_ID */ 623#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0 624#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F 625 626/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */ 627#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 628#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F 629 630/* TPC0_QM_ARB_MSG_AWUSER_31_11 */ 631#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 632#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF 633 634/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */ 635#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 636#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF 637#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 638#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 639 640/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ 641#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 642#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF 643#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 644#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 645 646/* TPC0_QM_ARB_BASE_LO */ 647#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0 648#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF 649 650/* TPC0_QM_ARB_BASE_HI */ 651#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0 652#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF 653 654/* TPC0_QM_ARB_STATE_STS */ 655#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0 656#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF 657 658/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */ 659#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 660#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F 661 662/* TPC0_QM_ARB_MSG_STS */ 663#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0 664#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1 665#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 666#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 667 668/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */ 669#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 670#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 671 672/* TPC0_QM_ARB_ERR_CAUSE */ 673#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 674#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 675#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 676#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 677#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 678#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 679 680/* TPC0_QM_ARB_ERR_MSG_EN */ 681#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 682#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 683#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 684#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 685#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 686#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 687 688/* TPC0_QM_ARB_ERR_STS_DRP */ 689#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 690#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 691 692/* TPC0_QM_ARB_MST_CRED_STS */ 693#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 694#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F 695 696/* TPC0_QM_CGM_CFG */ 697#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0 698#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF 699#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16 700#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 701#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 702#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 703#define TPC0_QM_CGM_CFG_EN_SHIFT 31 704#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000 705 706/* TPC0_QM_CGM_STS */ 707#define TPC0_QM_CGM_STS_ST_SHIFT 0 708#define TPC0_QM_CGM_STS_ST_MASK 0x3 709#define TPC0_QM_CGM_STS_CG_SHIFT 4 710#define TPC0_QM_CGM_STS_CG_MASK 0x10 711#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 712#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 713#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9 714#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200 715#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10 716#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400 717 718/* TPC0_QM_CGM_CFG1 */ 719#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0 720#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF 721 722/* TPC0_QM_LOCAL_RANGE_BASE */ 723#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 724#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF 725 726/* TPC0_QM_LOCAL_RANGE_SIZE */ 727#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 728#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF 729 730/* TPC0_QM_CSMR_STRICT_PRIO_CFG */ 731#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 732#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 733 734/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */ 735#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 736#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF 737#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 738#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 739 740/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */ 741#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 742#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 743#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 744#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 745 746/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */ 747#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 748#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF 749#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 750#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 751 752/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */ 753#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 754#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 755#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 756#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 757 758/* TPC0_QM_GLBL_AXCACHE */ 759#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0 760#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF 761#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16 762#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 763 764/* TPC0_QM_IND_GW_APB_CFG */ 765#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 766#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF 767#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 768#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 769 770/* TPC0_QM_IND_GW_APB_WDATA */ 771#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 772#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF 773 774/* TPC0_QM_IND_GW_APB_RDATA */ 775#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 776#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF 777 778/* TPC0_QM_IND_GW_APB_STATUS */ 779#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 780#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 781#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 782#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 783 784/* TPC0_QM_GLBL_ERR_ADDR_LO */ 785#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 786#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF 787 788/* TPC0_QM_GLBL_ERR_ADDR_HI */ 789#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 790#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF 791 792/* TPC0_QM_GLBL_ERR_WDATA */ 793#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 794#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF 795 796/* TPC0_QM_GLBL_MEM_INIT_BUSY */ 797#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 798#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF 799 800#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ 801