1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC2_QM0_REGS_H_ 14#define ASIC_REG_NIC2_QM0_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC2_QM0 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmNIC2_QM0_GLBL_CFG0 0xD60000 23 24#define mmNIC2_QM0_GLBL_CFG1 0xD60004 25 26#define mmNIC2_QM0_GLBL_PROT 0xD60008 27 28#define mmNIC2_QM0_GLBL_ERR_CFG 0xD6000C 29 30#define mmNIC2_QM0_GLBL_SECURE_PROPS_0 0xD60010 31 32#define mmNIC2_QM0_GLBL_SECURE_PROPS_1 0xD60014 33 34#define mmNIC2_QM0_GLBL_SECURE_PROPS_2 0xD60018 35 36#define mmNIC2_QM0_GLBL_SECURE_PROPS_3 0xD6001C 37 38#define mmNIC2_QM0_GLBL_SECURE_PROPS_4 0xD60020 39 40#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 0xD60024 41 42#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 0xD60028 43 44#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 0xD6002C 45 46#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 0xD60030 47 48#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 0xD60034 49 50#define mmNIC2_QM0_GLBL_STS0 0xD60038 51 52#define mmNIC2_QM0_GLBL_STS1_0 0xD60040 53 54#define mmNIC2_QM0_GLBL_STS1_1 0xD60044 55 56#define mmNIC2_QM0_GLBL_STS1_2 0xD60048 57 58#define mmNIC2_QM0_GLBL_STS1_3 0xD6004C 59 60#define mmNIC2_QM0_GLBL_STS1_4 0xD60050 61 62#define mmNIC2_QM0_GLBL_MSG_EN_0 0xD60054 63 64#define mmNIC2_QM0_GLBL_MSG_EN_1 0xD60058 65 66#define mmNIC2_QM0_GLBL_MSG_EN_2 0xD6005C 67 68#define mmNIC2_QM0_GLBL_MSG_EN_3 0xD60060 69 70#define mmNIC2_QM0_GLBL_MSG_EN_4 0xD60068 71 72#define mmNIC2_QM0_PQ_BASE_LO_0 0xD60070 73 74#define mmNIC2_QM0_PQ_BASE_LO_1 0xD60074 75 76#define mmNIC2_QM0_PQ_BASE_LO_2 0xD60078 77 78#define mmNIC2_QM0_PQ_BASE_LO_3 0xD6007C 79 80#define mmNIC2_QM0_PQ_BASE_HI_0 0xD60080 81 82#define mmNIC2_QM0_PQ_BASE_HI_1 0xD60084 83 84#define mmNIC2_QM0_PQ_BASE_HI_2 0xD60088 85 86#define mmNIC2_QM0_PQ_BASE_HI_3 0xD6008C 87 88#define mmNIC2_QM0_PQ_SIZE_0 0xD60090 89 90#define mmNIC2_QM0_PQ_SIZE_1 0xD60094 91 92#define mmNIC2_QM0_PQ_SIZE_2 0xD60098 93 94#define mmNIC2_QM0_PQ_SIZE_3 0xD6009C 95 96#define mmNIC2_QM0_PQ_PI_0 0xD600A0 97 98#define mmNIC2_QM0_PQ_PI_1 0xD600A4 99 100#define mmNIC2_QM0_PQ_PI_2 0xD600A8 101 102#define mmNIC2_QM0_PQ_PI_3 0xD600AC 103 104#define mmNIC2_QM0_PQ_CI_0 0xD600B0 105 106#define mmNIC2_QM0_PQ_CI_1 0xD600B4 107 108#define mmNIC2_QM0_PQ_CI_2 0xD600B8 109 110#define mmNIC2_QM0_PQ_CI_3 0xD600BC 111 112#define mmNIC2_QM0_PQ_CFG0_0 0xD600C0 113 114#define mmNIC2_QM0_PQ_CFG0_1 0xD600C4 115 116#define mmNIC2_QM0_PQ_CFG0_2 0xD600C8 117 118#define mmNIC2_QM0_PQ_CFG0_3 0xD600CC 119 120#define mmNIC2_QM0_PQ_CFG1_0 0xD600D0 121 122#define mmNIC2_QM0_PQ_CFG1_1 0xD600D4 123 124#define mmNIC2_QM0_PQ_CFG1_2 0xD600D8 125 126#define mmNIC2_QM0_PQ_CFG1_3 0xD600DC 127 128#define mmNIC2_QM0_PQ_ARUSER_31_11_0 0xD600E0 129 130#define mmNIC2_QM0_PQ_ARUSER_31_11_1 0xD600E4 131 132#define mmNIC2_QM0_PQ_ARUSER_31_11_2 0xD600E8 133 134#define mmNIC2_QM0_PQ_ARUSER_31_11_3 0xD600EC 135 136#define mmNIC2_QM0_PQ_STS0_0 0xD600F0 137 138#define mmNIC2_QM0_PQ_STS0_1 0xD600F4 139 140#define mmNIC2_QM0_PQ_STS0_2 0xD600F8 141 142#define mmNIC2_QM0_PQ_STS0_3 0xD600FC 143 144#define mmNIC2_QM0_PQ_STS1_0 0xD60100 145 146#define mmNIC2_QM0_PQ_STS1_1 0xD60104 147 148#define mmNIC2_QM0_PQ_STS1_2 0xD60108 149 150#define mmNIC2_QM0_PQ_STS1_3 0xD6010C 151 152#define mmNIC2_QM0_CQ_CFG0_0 0xD60110 153 154#define mmNIC2_QM0_CQ_CFG0_1 0xD60114 155 156#define mmNIC2_QM0_CQ_CFG0_2 0xD60118 157 158#define mmNIC2_QM0_CQ_CFG0_3 0xD6011C 159 160#define mmNIC2_QM0_CQ_CFG0_4 0xD60120 161 162#define mmNIC2_QM0_CQ_CFG1_0 0xD60124 163 164#define mmNIC2_QM0_CQ_CFG1_1 0xD60128 165 166#define mmNIC2_QM0_CQ_CFG1_2 0xD6012C 167 168#define mmNIC2_QM0_CQ_CFG1_3 0xD60130 169 170#define mmNIC2_QM0_CQ_CFG1_4 0xD60134 171 172#define mmNIC2_QM0_CQ_ARUSER_31_11_0 0xD60138 173 174#define mmNIC2_QM0_CQ_ARUSER_31_11_1 0xD6013C 175 176#define mmNIC2_QM0_CQ_ARUSER_31_11_2 0xD60140 177 178#define mmNIC2_QM0_CQ_ARUSER_31_11_3 0xD60144 179 180#define mmNIC2_QM0_CQ_ARUSER_31_11_4 0xD60148 181 182#define mmNIC2_QM0_CQ_STS0_0 0xD6014C 183 184#define mmNIC2_QM0_CQ_STS0_1 0xD60150 185 186#define mmNIC2_QM0_CQ_STS0_2 0xD60154 187 188#define mmNIC2_QM0_CQ_STS0_3 0xD60158 189 190#define mmNIC2_QM0_CQ_STS0_4 0xD6015C 191 192#define mmNIC2_QM0_CQ_STS1_0 0xD60160 193 194#define mmNIC2_QM0_CQ_STS1_1 0xD60164 195 196#define mmNIC2_QM0_CQ_STS1_2 0xD60168 197 198#define mmNIC2_QM0_CQ_STS1_3 0xD6016C 199 200#define mmNIC2_QM0_CQ_STS1_4 0xD60170 201 202#define mmNIC2_QM0_CQ_PTR_LO_0 0xD60174 203 204#define mmNIC2_QM0_CQ_PTR_HI_0 0xD60178 205 206#define mmNIC2_QM0_CQ_TSIZE_0 0xD6017C 207 208#define mmNIC2_QM0_CQ_CTL_0 0xD60180 209 210#define mmNIC2_QM0_CQ_PTR_LO_1 0xD60184 211 212#define mmNIC2_QM0_CQ_PTR_HI_1 0xD60188 213 214#define mmNIC2_QM0_CQ_TSIZE_1 0xD6018C 215 216#define mmNIC2_QM0_CQ_CTL_1 0xD60190 217 218#define mmNIC2_QM0_CQ_PTR_LO_2 0xD60194 219 220#define mmNIC2_QM0_CQ_PTR_HI_2 0xD60198 221 222#define mmNIC2_QM0_CQ_TSIZE_2 0xD6019C 223 224#define mmNIC2_QM0_CQ_CTL_2 0xD601A0 225 226#define mmNIC2_QM0_CQ_PTR_LO_3 0xD601A4 227 228#define mmNIC2_QM0_CQ_PTR_HI_3 0xD601A8 229 230#define mmNIC2_QM0_CQ_TSIZE_3 0xD601AC 231 232#define mmNIC2_QM0_CQ_CTL_3 0xD601B0 233 234#define mmNIC2_QM0_CQ_PTR_LO_4 0xD601B4 235 236#define mmNIC2_QM0_CQ_PTR_HI_4 0xD601B8 237 238#define mmNIC2_QM0_CQ_TSIZE_4 0xD601BC 239 240#define mmNIC2_QM0_CQ_CTL_4 0xD601C0 241 242#define mmNIC2_QM0_CQ_PTR_LO_STS_0 0xD601C4 243 244#define mmNIC2_QM0_CQ_PTR_LO_STS_1 0xD601C8 245 246#define mmNIC2_QM0_CQ_PTR_LO_STS_2 0xD601CC 247 248#define mmNIC2_QM0_CQ_PTR_LO_STS_3 0xD601D0 249 250#define mmNIC2_QM0_CQ_PTR_LO_STS_4 0xD601D4 251 252#define mmNIC2_QM0_CQ_PTR_HI_STS_0 0xD601D8 253 254#define mmNIC2_QM0_CQ_PTR_HI_STS_1 0xD601DC 255 256#define mmNIC2_QM0_CQ_PTR_HI_STS_2 0xD601E0 257 258#define mmNIC2_QM0_CQ_PTR_HI_STS_3 0xD601E4 259 260#define mmNIC2_QM0_CQ_PTR_HI_STS_4 0xD601E8 261 262#define mmNIC2_QM0_CQ_TSIZE_STS_0 0xD601EC 263 264#define mmNIC2_QM0_CQ_TSIZE_STS_1 0xD601F0 265 266#define mmNIC2_QM0_CQ_TSIZE_STS_2 0xD601F4 267 268#define mmNIC2_QM0_CQ_TSIZE_STS_3 0xD601F8 269 270#define mmNIC2_QM0_CQ_TSIZE_STS_4 0xD601FC 271 272#define mmNIC2_QM0_CQ_CTL_STS_0 0xD60200 273 274#define mmNIC2_QM0_CQ_CTL_STS_1 0xD60204 275 276#define mmNIC2_QM0_CQ_CTL_STS_2 0xD60208 277 278#define mmNIC2_QM0_CQ_CTL_STS_3 0xD6020C 279 280#define mmNIC2_QM0_CQ_CTL_STS_4 0xD60210 281 282#define mmNIC2_QM0_CQ_IFIFO_CNT_0 0xD60214 283 284#define mmNIC2_QM0_CQ_IFIFO_CNT_1 0xD60218 285 286#define mmNIC2_QM0_CQ_IFIFO_CNT_2 0xD6021C 287 288#define mmNIC2_QM0_CQ_IFIFO_CNT_3 0xD60220 289 290#define mmNIC2_QM0_CQ_IFIFO_CNT_4 0xD60224 291 292#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD60228 293 294#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD6022C 295 296#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD60230 297 298#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD60234 299 300#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD60238 301 302#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD6023C 303 304#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD60240 305 306#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD60244 307 308#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD60248 309 310#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD6024C 311 312#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD60250 313 314#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD60254 315 316#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD60258 317 318#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD6025C 319 320#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD60260 321 322#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD60264 323 324#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD60268 325 326#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD6026C 327 328#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD60270 329 330#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD60274 331 332#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD60278 333 334#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD6027C 335 336#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD60280 337 338#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD60284 339 340#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD60288 341 342#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD6028C 343 344#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD60290 345 346#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD60294 347 348#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD60298 349 350#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD6029C 351 352#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD602A0 353 354#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD602A4 355 356#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD602A8 357 358#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD602AC 359 360#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD602B0 361 362#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD602B4 363 364#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD602B8 365 366#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD602BC 367 368#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD602C0 369 370#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD602C4 371 372#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD602C8 373 374#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD602CC 375 376#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD602D0 377 378#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD602D4 379 380#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD602D8 381 382#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD602E0 383 384#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD602E4 385 386#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD602E8 387 388#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD602EC 389 390#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD602F0 391 392#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD602F4 393 394#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD602F8 395 396#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD602FC 397 398#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD60300 399 400#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD60304 401 402#define mmNIC2_QM0_CP_FENCE0_RDATA_0 0xD60308 403 404#define mmNIC2_QM0_CP_FENCE0_RDATA_1 0xD6030C 405 406#define mmNIC2_QM0_CP_FENCE0_RDATA_2 0xD60310 407 408#define mmNIC2_QM0_CP_FENCE0_RDATA_3 0xD60314 409 410#define mmNIC2_QM0_CP_FENCE0_RDATA_4 0xD60318 411 412#define mmNIC2_QM0_CP_FENCE1_RDATA_0 0xD6031C 413 414#define mmNIC2_QM0_CP_FENCE1_RDATA_1 0xD60320 415 416#define mmNIC2_QM0_CP_FENCE1_RDATA_2 0xD60324 417 418#define mmNIC2_QM0_CP_FENCE1_RDATA_3 0xD60328 419 420#define mmNIC2_QM0_CP_FENCE1_RDATA_4 0xD6032C 421 422#define mmNIC2_QM0_CP_FENCE2_RDATA_0 0xD60330 423 424#define mmNIC2_QM0_CP_FENCE2_RDATA_1 0xD60334 425 426#define mmNIC2_QM0_CP_FENCE2_RDATA_2 0xD60338 427 428#define mmNIC2_QM0_CP_FENCE2_RDATA_3 0xD6033C 429 430#define mmNIC2_QM0_CP_FENCE2_RDATA_4 0xD60340 431 432#define mmNIC2_QM0_CP_FENCE3_RDATA_0 0xD60344 433 434#define mmNIC2_QM0_CP_FENCE3_RDATA_1 0xD60348 435 436#define mmNIC2_QM0_CP_FENCE3_RDATA_2 0xD6034C 437 438#define mmNIC2_QM0_CP_FENCE3_RDATA_3 0xD60350 439 440#define mmNIC2_QM0_CP_FENCE3_RDATA_4 0xD60354 441 442#define mmNIC2_QM0_CP_FENCE0_CNT_0 0xD60358 443 444#define mmNIC2_QM0_CP_FENCE0_CNT_1 0xD6035C 445 446#define mmNIC2_QM0_CP_FENCE0_CNT_2 0xD60360 447 448#define mmNIC2_QM0_CP_FENCE0_CNT_3 0xD60364 449 450#define mmNIC2_QM0_CP_FENCE0_CNT_4 0xD60368 451 452#define mmNIC2_QM0_CP_FENCE1_CNT_0 0xD6036C 453 454#define mmNIC2_QM0_CP_FENCE1_CNT_1 0xD60370 455 456#define mmNIC2_QM0_CP_FENCE1_CNT_2 0xD60374 457 458#define mmNIC2_QM0_CP_FENCE1_CNT_3 0xD60378 459 460#define mmNIC2_QM0_CP_FENCE1_CNT_4 0xD6037C 461 462#define mmNIC2_QM0_CP_FENCE2_CNT_0 0xD60380 463 464#define mmNIC2_QM0_CP_FENCE2_CNT_1 0xD60384 465 466#define mmNIC2_QM0_CP_FENCE2_CNT_2 0xD60388 467 468#define mmNIC2_QM0_CP_FENCE2_CNT_3 0xD6038C 469 470#define mmNIC2_QM0_CP_FENCE2_CNT_4 0xD60390 471 472#define mmNIC2_QM0_CP_FENCE3_CNT_0 0xD60394 473 474#define mmNIC2_QM0_CP_FENCE3_CNT_1 0xD60398 475 476#define mmNIC2_QM0_CP_FENCE3_CNT_2 0xD6039C 477 478#define mmNIC2_QM0_CP_FENCE3_CNT_3 0xD603A0 479 480#define mmNIC2_QM0_CP_FENCE3_CNT_4 0xD603A4 481 482#define mmNIC2_QM0_CP_STS_0 0xD603A8 483 484#define mmNIC2_QM0_CP_STS_1 0xD603AC 485 486#define mmNIC2_QM0_CP_STS_2 0xD603B0 487 488#define mmNIC2_QM0_CP_STS_3 0xD603B4 489 490#define mmNIC2_QM0_CP_STS_4 0xD603B8 491 492#define mmNIC2_QM0_CP_CURRENT_INST_LO_0 0xD603BC 493 494#define mmNIC2_QM0_CP_CURRENT_INST_LO_1 0xD603C0 495 496#define mmNIC2_QM0_CP_CURRENT_INST_LO_2 0xD603C4 497 498#define mmNIC2_QM0_CP_CURRENT_INST_LO_3 0xD603C8 499 500#define mmNIC2_QM0_CP_CURRENT_INST_LO_4 0xD603CC 501 502#define mmNIC2_QM0_CP_CURRENT_INST_HI_0 0xD603D0 503 504#define mmNIC2_QM0_CP_CURRENT_INST_HI_1 0xD603D4 505 506#define mmNIC2_QM0_CP_CURRENT_INST_HI_2 0xD603D8 507 508#define mmNIC2_QM0_CP_CURRENT_INST_HI_3 0xD603DC 509 510#define mmNIC2_QM0_CP_CURRENT_INST_HI_4 0xD603E0 511 512#define mmNIC2_QM0_CP_BARRIER_CFG_0 0xD603F4 513 514#define mmNIC2_QM0_CP_BARRIER_CFG_1 0xD603F8 515 516#define mmNIC2_QM0_CP_BARRIER_CFG_2 0xD603FC 517 518#define mmNIC2_QM0_CP_BARRIER_CFG_3 0xD60400 519 520#define mmNIC2_QM0_CP_BARRIER_CFG_4 0xD60404 521 522#define mmNIC2_QM0_CP_DBG_0_0 0xD60408 523 524#define mmNIC2_QM0_CP_DBG_0_1 0xD6040C 525 526#define mmNIC2_QM0_CP_DBG_0_2 0xD60410 527 528#define mmNIC2_QM0_CP_DBG_0_3 0xD60414 529 530#define mmNIC2_QM0_CP_DBG_0_4 0xD60418 531 532#define mmNIC2_QM0_CP_ARUSER_31_11_0 0xD6041C 533 534#define mmNIC2_QM0_CP_ARUSER_31_11_1 0xD60420 535 536#define mmNIC2_QM0_CP_ARUSER_31_11_2 0xD60424 537 538#define mmNIC2_QM0_CP_ARUSER_31_11_3 0xD60428 539 540#define mmNIC2_QM0_CP_ARUSER_31_11_4 0xD6042C 541 542#define mmNIC2_QM0_CP_AWUSER_31_11_0 0xD60430 543 544#define mmNIC2_QM0_CP_AWUSER_31_11_1 0xD60434 545 546#define mmNIC2_QM0_CP_AWUSER_31_11_2 0xD60438 547 548#define mmNIC2_QM0_CP_AWUSER_31_11_3 0xD6043C 549 550#define mmNIC2_QM0_CP_AWUSER_31_11_4 0xD60440 551 552#define mmNIC2_QM0_ARB_CFG_0 0xD60A00 553 554#define mmNIC2_QM0_ARB_CHOISE_Q_PUSH 0xD60A04 555 556#define mmNIC2_QM0_ARB_WRR_WEIGHT_0 0xD60A08 557 558#define mmNIC2_QM0_ARB_WRR_WEIGHT_1 0xD60A0C 559 560#define mmNIC2_QM0_ARB_WRR_WEIGHT_2 0xD60A10 561 562#define mmNIC2_QM0_ARB_WRR_WEIGHT_3 0xD60A14 563 564#define mmNIC2_QM0_ARB_CFG_1 0xD60A18 565 566#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 0xD60A20 567 568#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 0xD60A24 569 570#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 0xD60A28 571 572#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 0xD60A2C 573 574#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 0xD60A30 575 576#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 0xD60A34 577 578#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 0xD60A38 579 580#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 0xD60A3C 581 582#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 0xD60A40 583 584#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 0xD60A44 585 586#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 0xD60A48 587 588#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 0xD60A4C 589 590#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 0xD60A50 591 592#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 0xD60A54 593 594#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 0xD60A58 595 596#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 0xD60A5C 597 598#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 0xD60A60 599 600#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 0xD60A64 601 602#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 0xD60A68 603 604#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 0xD60A6C 605 606#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 0xD60A70 607 608#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 0xD60A74 609 610#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 0xD60A78 611 612#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 0xD60A7C 613 614#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 0xD60A80 615 616#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 0xD60A84 617 618#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 0xD60A88 619 620#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 0xD60A8C 621 622#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 0xD60A90 623 624#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 0xD60A94 625 626#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 0xD60A98 627 628#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 0xD60A9C 629 630#define mmNIC2_QM0_ARB_MST_CRED_INC 0xD60AA0 631 632#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD60AA4 633 634#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD60AA8 635 636#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD60AAC 637 638#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD60AB0 639 640#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD60AB4 641 642#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD60AB8 643 644#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD60ABC 645 646#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD60AC0 647 648#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD60AC4 649 650#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD60AC8 651 652#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD60ACC 653 654#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD60AD0 655 656#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD60AD4 657 658#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD60AD8 659 660#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD60ADC 661 662#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD60AE0 663 664#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD60AE4 665 666#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD60AE8 667 668#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD60AEC 669 670#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD60AF0 671 672#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD60AF4 673 674#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD60AF8 675 676#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD60AFC 677 678#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD60B00 679 680#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD60B04 681 682#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD60B08 683 684#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD60B0C 685 686#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD60B10 687 688#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD60B14 689 690#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD60B18 691 692#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD60B1C 693 694#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD60B20 695 696#define mmNIC2_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD60B28 697 698#define mmNIC2_QM0_ARB_MST_SLAVE_EN 0xD60B2C 699 700#define mmNIC2_QM0_ARB_MST_QUIET_PER 0xD60B34 701 702#define mmNIC2_QM0_ARB_SLV_CHOISE_WDT 0xD60B38 703 704#define mmNIC2_QM0_ARB_SLV_ID 0xD60B3C 705 706#define mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT 0xD60B44 707 708#define mmNIC2_QM0_ARB_MSG_AWUSER_31_11 0xD60B48 709 710#define mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD60B4C 711 712#define mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD60B50 713 714#define mmNIC2_QM0_ARB_BASE_LO 0xD60B54 715 716#define mmNIC2_QM0_ARB_BASE_HI 0xD60B58 717 718#define mmNIC2_QM0_ARB_STATE_STS 0xD60B80 719 720#define mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS 0xD60B84 721 722#define mmNIC2_QM0_ARB_MSG_STS 0xD60B88 723 724#define mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD60B8C 725 726#define mmNIC2_QM0_ARB_ERR_CAUSE 0xD60B9C 727 728#define mmNIC2_QM0_ARB_ERR_MSG_EN 0xD60BA0 729 730#define mmNIC2_QM0_ARB_ERR_STS_DRP 0xD60BA8 731 732#define mmNIC2_QM0_ARB_MST_CRED_STS_0 0xD60BB0 733 734#define mmNIC2_QM0_ARB_MST_CRED_STS_1 0xD60BB4 735 736#define mmNIC2_QM0_ARB_MST_CRED_STS_2 0xD60BB8 737 738#define mmNIC2_QM0_ARB_MST_CRED_STS_3 0xD60BBC 739 740#define mmNIC2_QM0_ARB_MST_CRED_STS_4 0xD60BC0 741 742#define mmNIC2_QM0_ARB_MST_CRED_STS_5 0xD60BC4 743 744#define mmNIC2_QM0_ARB_MST_CRED_STS_6 0xD60BC8 745 746#define mmNIC2_QM0_ARB_MST_CRED_STS_7 0xD60BCC 747 748#define mmNIC2_QM0_ARB_MST_CRED_STS_8 0xD60BD0 749 750#define mmNIC2_QM0_ARB_MST_CRED_STS_9 0xD60BD4 751 752#define mmNIC2_QM0_ARB_MST_CRED_STS_10 0xD60BD8 753 754#define mmNIC2_QM0_ARB_MST_CRED_STS_11 0xD60BDC 755 756#define mmNIC2_QM0_ARB_MST_CRED_STS_12 0xD60BE0 757 758#define mmNIC2_QM0_ARB_MST_CRED_STS_13 0xD60BE4 759 760#define mmNIC2_QM0_ARB_MST_CRED_STS_14 0xD60BE8 761 762#define mmNIC2_QM0_ARB_MST_CRED_STS_15 0xD60BEC 763 764#define mmNIC2_QM0_ARB_MST_CRED_STS_16 0xD60BF0 765 766#define mmNIC2_QM0_ARB_MST_CRED_STS_17 0xD60BF4 767 768#define mmNIC2_QM0_ARB_MST_CRED_STS_18 0xD60BF8 769 770#define mmNIC2_QM0_ARB_MST_CRED_STS_19 0xD60BFC 771 772#define mmNIC2_QM0_ARB_MST_CRED_STS_20 0xD60C00 773 774#define mmNIC2_QM0_ARB_MST_CRED_STS_21 0xD60C04 775 776#define mmNIC2_QM0_ARB_MST_CRED_STS_22 0xD60C08 777 778#define mmNIC2_QM0_ARB_MST_CRED_STS_23 0xD60C0C 779 780#define mmNIC2_QM0_ARB_MST_CRED_STS_24 0xD60C10 781 782#define mmNIC2_QM0_ARB_MST_CRED_STS_25 0xD60C14 783 784#define mmNIC2_QM0_ARB_MST_CRED_STS_26 0xD60C18 785 786#define mmNIC2_QM0_ARB_MST_CRED_STS_27 0xD60C1C 787 788#define mmNIC2_QM0_ARB_MST_CRED_STS_28 0xD60C20 789 790#define mmNIC2_QM0_ARB_MST_CRED_STS_29 0xD60C24 791 792#define mmNIC2_QM0_ARB_MST_CRED_STS_30 0xD60C28 793 794#define mmNIC2_QM0_ARB_MST_CRED_STS_31 0xD60C2C 795 796#define mmNIC2_QM0_CGM_CFG 0xD60C70 797 798#define mmNIC2_QM0_CGM_STS 0xD60C74 799 800#define mmNIC2_QM0_CGM_CFG1 0xD60C78 801 802#define mmNIC2_QM0_LOCAL_RANGE_BASE 0xD60C80 803 804#define mmNIC2_QM0_LOCAL_RANGE_SIZE 0xD60C84 805 806#define mmNIC2_QM0_CSMR_STRICT_PRIO_CFG 0xD60C90 807 808#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 0xD60C94 809 810#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 0xD60C98 811 812#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 0xD60C9C 813 814#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 0xD60CA0 815 816#define mmNIC2_QM0_GLBL_AXCACHE 0xD60CA4 817 818#define mmNIC2_QM0_IND_GW_APB_CFG 0xD60CB0 819 820#define mmNIC2_QM0_IND_GW_APB_WDATA 0xD60CB4 821 822#define mmNIC2_QM0_IND_GW_APB_RDATA 0xD60CB8 823 824#define mmNIC2_QM0_IND_GW_APB_STATUS 0xD60CBC 825 826#define mmNIC2_QM0_GLBL_ERR_ADDR_LO 0xD60CD0 827 828#define mmNIC2_QM0_GLBL_ERR_ADDR_HI 0xD60CD4 829 830#define mmNIC2_QM0_GLBL_ERR_WDATA 0xD60CD8 831 832#define mmNIC2_QM0_GLBL_MEM_INIT_BUSY 0xD60D00 833 834#endif /* ASIC_REG_NIC2_QM0_REGS_H_ */ 835