1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA7_CORE_REGS_H_ 14#define ASIC_REG_DMA7_CORE_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA7_CORE (Prototype: DMA_CORE) 19 ***************************************** 20 */ 21 22#define mmDMA7_CORE_CFG_0 0x5E0000 23 24#define mmDMA7_CORE_CFG_1 0x5E0004 25 26#define mmDMA7_CORE_LBW_MAX_OUTSTAND 0x5E0008 27 28#define mmDMA7_CORE_SRC_BASE_LO 0x5E0014 29 30#define mmDMA7_CORE_SRC_BASE_HI 0x5E0018 31 32#define mmDMA7_CORE_DST_BASE_LO 0x5E001C 33 34#define mmDMA7_CORE_DST_BASE_HI 0x5E0020 35 36#define mmDMA7_CORE_SRC_TSIZE_1 0x5E002C 37 38#define mmDMA7_CORE_SRC_STRIDE_1 0x5E0030 39 40#define mmDMA7_CORE_SRC_TSIZE_2 0x5E0034 41 42#define mmDMA7_CORE_SRC_STRIDE_2 0x5E0038 43 44#define mmDMA7_CORE_SRC_TSIZE_3 0x5E003C 45 46#define mmDMA7_CORE_SRC_STRIDE_3 0x5E0040 47 48#define mmDMA7_CORE_SRC_TSIZE_4 0x5E0044 49 50#define mmDMA7_CORE_SRC_STRIDE_4 0x5E0048 51 52#define mmDMA7_CORE_SRC_TSIZE_0 0x5E004C 53 54#define mmDMA7_CORE_DST_TSIZE_1 0x5E0054 55 56#define mmDMA7_CORE_DST_STRIDE_1 0x5E0058 57 58#define mmDMA7_CORE_DST_TSIZE_2 0x5E005C 59 60#define mmDMA7_CORE_DST_STRIDE_2 0x5E0060 61 62#define mmDMA7_CORE_DST_TSIZE_3 0x5E0064 63 64#define mmDMA7_CORE_DST_STRIDE_3 0x5E0068 65 66#define mmDMA7_CORE_DST_TSIZE_4 0x5E006C 67 68#define mmDMA7_CORE_DST_STRIDE_4 0x5E0070 69 70#define mmDMA7_CORE_DST_TSIZE_0 0x5E0074 71 72#define mmDMA7_CORE_COMMIT 0x5E0078 73 74#define mmDMA7_CORE_WR_COMP_WDATA 0x5E007C 75 76#define mmDMA7_CORE_WR_COMP_ADDR_LO 0x5E0080 77 78#define mmDMA7_CORE_WR_COMP_ADDR_HI 0x5E0084 79 80#define mmDMA7_CORE_WR_COMP_AWUSER_31_11 0x5E0088 81 82#define mmDMA7_CORE_TE_NUMROWS 0x5E0094 83 84#define mmDMA7_CORE_PROT 0x5E00B8 85 86#define mmDMA7_CORE_SECURE_PROPS 0x5E00F0 87 88#define mmDMA7_CORE_NON_SECURE_PROPS 0x5E00F4 89 90#define mmDMA7_CORE_RD_MAX_OUTSTAND 0x5E0100 91 92#define mmDMA7_CORE_RD_MAX_SIZE 0x5E0104 93 94#define mmDMA7_CORE_RD_ARCACHE 0x5E0108 95 96#define mmDMA7_CORE_RD_ARUSER_31_11 0x5E0110 97 98#define mmDMA7_CORE_RD_INFLIGHTS 0x5E0114 99 100#define mmDMA7_CORE_WR_MAX_OUTSTAND 0x5E0120 101 102#define mmDMA7_CORE_WR_MAX_AWID 0x5E0124 103 104#define mmDMA7_CORE_WR_AWCACHE 0x5E0128 105 106#define mmDMA7_CORE_WR_AWUSER_31_11 0x5E0130 107 108#define mmDMA7_CORE_WR_INFLIGHTS 0x5E0134 109 110#define mmDMA7_CORE_RD_RATE_LIM_CFG_0 0x5E0150 111 112#define mmDMA7_CORE_RD_RATE_LIM_CFG_1 0x5E0154 113 114#define mmDMA7_CORE_WR_RATE_LIM_CFG_0 0x5E0158 115 116#define mmDMA7_CORE_WR_RATE_LIM_CFG_1 0x5E015C 117 118#define mmDMA7_CORE_ERR_CFG 0x5E0160 119 120#define mmDMA7_CORE_ERR_CAUSE 0x5E0164 121 122#define mmDMA7_CORE_ERRMSG_ADDR_LO 0x5E0170 123 124#define mmDMA7_CORE_ERRMSG_ADDR_HI 0x5E0174 125 126#define mmDMA7_CORE_ERRMSG_WDATA 0x5E0178 127 128#define mmDMA7_CORE_STS0 0x5E0190 129 130#define mmDMA7_CORE_STS1 0x5E0194 131 132#define mmDMA7_CORE_RD_DBGMEM_ADD 0x5E0200 133 134#define mmDMA7_CORE_RD_DBGMEM_DATA_WR 0x5E0204 135 136#define mmDMA7_CORE_RD_DBGMEM_DATA_RD 0x5E0208 137 138#define mmDMA7_CORE_RD_DBGMEM_CTRL 0x5E020C 139 140#define mmDMA7_CORE_RD_DBGMEM_RC 0x5E0210 141 142#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT 0x5E0220 143 144#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT 0x5E0224 145 146#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT 0x5E0228 147 148#define mmDMA7_CORE_DBG_DESC_CNT 0x5E022C 149 150#define mmDMA7_CORE_DBG_STS 0x5E0230 151 152#define mmDMA7_CORE_DBG_RD_DESC_ID 0x5E0234 153 154#define mmDMA7_CORE_DBG_WR_DESC_ID 0x5E0238 155 156#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */ 157