1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA5_QM_REGS_H_ 14#define ASIC_REG_DMA5_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA5_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmDMA5_QM_GLBL_CFG0 0x5A8000 23 24#define mmDMA5_QM_GLBL_CFG1 0x5A8004 25 26#define mmDMA5_QM_GLBL_PROT 0x5A8008 27 28#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C 29 30#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010 31 32#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014 33 34#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018 35 36#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C 37 38#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020 39 40#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024 41 42#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028 43 44#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C 45 46#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030 47 48#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034 49 50#define mmDMA5_QM_GLBL_STS0 0x5A8038 51 52#define mmDMA5_QM_GLBL_STS1_0 0x5A8040 53 54#define mmDMA5_QM_GLBL_STS1_1 0x5A8044 55 56#define mmDMA5_QM_GLBL_STS1_2 0x5A8048 57 58#define mmDMA5_QM_GLBL_STS1_3 0x5A804C 59 60#define mmDMA5_QM_GLBL_STS1_4 0x5A8050 61 62#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054 63 64#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058 65 66#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C 67 68#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060 69 70#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068 71 72#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070 73 74#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074 75 76#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078 77 78#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C 79 80#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080 81 82#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084 83 84#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088 85 86#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C 87 88#define mmDMA5_QM_PQ_SIZE_0 0x5A8090 89 90#define mmDMA5_QM_PQ_SIZE_1 0x5A8094 91 92#define mmDMA5_QM_PQ_SIZE_2 0x5A8098 93 94#define mmDMA5_QM_PQ_SIZE_3 0x5A809C 95 96#define mmDMA5_QM_PQ_PI_0 0x5A80A0 97 98#define mmDMA5_QM_PQ_PI_1 0x5A80A4 99 100#define mmDMA5_QM_PQ_PI_2 0x5A80A8 101 102#define mmDMA5_QM_PQ_PI_3 0x5A80AC 103 104#define mmDMA5_QM_PQ_CI_0 0x5A80B0 105 106#define mmDMA5_QM_PQ_CI_1 0x5A80B4 107 108#define mmDMA5_QM_PQ_CI_2 0x5A80B8 109 110#define mmDMA5_QM_PQ_CI_3 0x5A80BC 111 112#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0 113 114#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4 115 116#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8 117 118#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC 119 120#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0 121 122#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4 123 124#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8 125 126#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC 127 128#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0 129 130#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4 131 132#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8 133 134#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC 135 136#define mmDMA5_QM_PQ_STS0_0 0x5A80F0 137 138#define mmDMA5_QM_PQ_STS0_1 0x5A80F4 139 140#define mmDMA5_QM_PQ_STS0_2 0x5A80F8 141 142#define mmDMA5_QM_PQ_STS0_3 0x5A80FC 143 144#define mmDMA5_QM_PQ_STS1_0 0x5A8100 145 146#define mmDMA5_QM_PQ_STS1_1 0x5A8104 147 148#define mmDMA5_QM_PQ_STS1_2 0x5A8108 149 150#define mmDMA5_QM_PQ_STS1_3 0x5A810C 151 152#define mmDMA5_QM_CQ_CFG0_0 0x5A8110 153 154#define mmDMA5_QM_CQ_CFG0_1 0x5A8114 155 156#define mmDMA5_QM_CQ_CFG0_2 0x5A8118 157 158#define mmDMA5_QM_CQ_CFG0_3 0x5A811C 159 160#define mmDMA5_QM_CQ_CFG0_4 0x5A8120 161 162#define mmDMA5_QM_CQ_CFG1_0 0x5A8124 163 164#define mmDMA5_QM_CQ_CFG1_1 0x5A8128 165 166#define mmDMA5_QM_CQ_CFG1_2 0x5A812C 167 168#define mmDMA5_QM_CQ_CFG1_3 0x5A8130 169 170#define mmDMA5_QM_CQ_CFG1_4 0x5A8134 171 172#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138 173 174#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C 175 176#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140 177 178#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144 179 180#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148 181 182#define mmDMA5_QM_CQ_STS0_0 0x5A814C 183 184#define mmDMA5_QM_CQ_STS0_1 0x5A8150 185 186#define mmDMA5_QM_CQ_STS0_2 0x5A8154 187 188#define mmDMA5_QM_CQ_STS0_3 0x5A8158 189 190#define mmDMA5_QM_CQ_STS0_4 0x5A815C 191 192#define mmDMA5_QM_CQ_STS1_0 0x5A8160 193 194#define mmDMA5_QM_CQ_STS1_1 0x5A8164 195 196#define mmDMA5_QM_CQ_STS1_2 0x5A8168 197 198#define mmDMA5_QM_CQ_STS1_3 0x5A816C 199 200#define mmDMA5_QM_CQ_STS1_4 0x5A8170 201 202#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174 203 204#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178 205 206#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C 207 208#define mmDMA5_QM_CQ_CTL_0 0x5A8180 209 210#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184 211 212#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188 213 214#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C 215 216#define mmDMA5_QM_CQ_CTL_1 0x5A8190 217 218#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194 219 220#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198 221 222#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C 223 224#define mmDMA5_QM_CQ_CTL_2 0x5A81A0 225 226#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4 227 228#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8 229 230#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC 231 232#define mmDMA5_QM_CQ_CTL_3 0x5A81B0 233 234#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4 235 236#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8 237 238#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC 239 240#define mmDMA5_QM_CQ_CTL_4 0x5A81C0 241 242#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4 243 244#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8 245 246#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC 247 248#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0 249 250#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4 251 252#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8 253 254#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC 255 256#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0 257 258#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4 259 260#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8 261 262#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC 263 264#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0 265 266#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4 267 268#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8 269 270#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC 271 272#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200 273 274#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204 275 276#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208 277 278#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C 279 280#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210 281 282#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214 283 284#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218 285 286#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C 287 288#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220 289 290#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224 291 292#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228 293 294#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C 295 296#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230 297 298#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234 299 300#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238 301 302#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C 303 304#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240 305 306#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244 307 308#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248 309 310#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C 311 312#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250 313 314#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254 315 316#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258 317 318#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C 319 320#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260 321 322#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264 323 324#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268 325 326#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C 327 328#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270 329 330#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274 331 332#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278 333 334#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C 335 336#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280 337 338#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284 339 340#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288 341 342#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C 343 344#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290 345 346#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294 347 348#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298 349 350#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C 351 352#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0 353 354#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4 355 356#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8 357 358#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC 359 360#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0 361 362#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4 363 364#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8 365 366#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC 367 368#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0 369 370#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4 371 372#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8 373 374#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC 375 376#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0 377 378#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4 379 380#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8 381 382#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0 383 384#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4 385 386#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8 387 388#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC 389 390#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0 391 392#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4 393 394#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8 395 396#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC 397 398#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300 399 400#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304 401 402#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308 403 404#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C 405 406#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310 407 408#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314 409 410#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318 411 412#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C 413 414#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320 415 416#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324 417 418#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328 419 420#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C 421 422#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330 423 424#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334 425 426#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338 427 428#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C 429 430#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340 431 432#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344 433 434#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348 435 436#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C 437 438#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350 439 440#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354 441 442#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358 443 444#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C 445 446#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360 447 448#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364 449 450#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368 451 452#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C 453 454#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370 455 456#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374 457 458#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378 459 460#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C 461 462#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380 463 464#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384 465 466#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388 467 468#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C 469 470#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390 471 472#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394 473 474#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398 475 476#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C 477 478#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0 479 480#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4 481 482#define mmDMA5_QM_CP_STS_0 0x5A83A8 483 484#define mmDMA5_QM_CP_STS_1 0x5A83AC 485 486#define mmDMA5_QM_CP_STS_2 0x5A83B0 487 488#define mmDMA5_QM_CP_STS_3 0x5A83B4 489 490#define mmDMA5_QM_CP_STS_4 0x5A83B8 491 492#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC 493 494#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0 495 496#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4 497 498#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8 499 500#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC 501 502#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0 503 504#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4 505 506#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8 507 508#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC 509 510#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0 511 512#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4 513 514#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8 515 516#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC 517 518#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400 519 520#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404 521 522#define mmDMA5_QM_CP_DBG_0_0 0x5A8408 523 524#define mmDMA5_QM_CP_DBG_0_1 0x5A840C 525 526#define mmDMA5_QM_CP_DBG_0_2 0x5A8410 527 528#define mmDMA5_QM_CP_DBG_0_3 0x5A8414 529 530#define mmDMA5_QM_CP_DBG_0_4 0x5A8418 531 532#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C 533 534#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420 535 536#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424 537 538#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428 539 540#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C 541 542#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430 543 544#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434 545 546#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438 547 548#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C 549 550#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440 551 552#define mmDMA5_QM_ARB_CFG_0 0x5A8A00 553 554#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04 555 556#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08 557 558#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C 559 560#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10 561 562#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14 563 564#define mmDMA5_QM_ARB_CFG_1 0x5A8A18 565 566#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20 567 568#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24 569 570#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28 571 572#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C 573 574#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30 575 576#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34 577 578#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38 579 580#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C 581 582#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40 583 584#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44 585 586#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48 587 588#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C 589 590#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50 591 592#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54 593 594#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58 595 596#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C 597 598#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60 599 600#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64 601 602#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68 603 604#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C 605 606#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70 607 608#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74 609 610#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78 611 612#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C 613 614#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80 615 616#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84 617 618#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88 619 620#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C 621 622#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90 623 624#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94 625 626#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98 627 628#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C 629 630#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0 631 632#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4 633 634#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8 635 636#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC 637 638#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0 639 640#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4 641 642#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8 643 644#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC 645 646#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0 647 648#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4 649 650#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8 651 652#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC 653 654#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0 655 656#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4 657 658#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8 659 660#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC 661 662#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0 663 664#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4 665 666#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8 667 668#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC 669 670#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0 671 672#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4 673 674#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8 675 676#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC 677 678#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00 679 680#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04 681 682#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08 683 684#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C 685 686#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10 687 688#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14 689 690#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18 691 692#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C 693 694#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20 695 696#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28 697 698#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C 699 700#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34 701 702#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38 703 704#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C 705 706#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44 707 708#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48 709 710#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C 711 712#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50 713 714#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54 715 716#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58 717 718#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80 719 720#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84 721 722#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88 723 724#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C 725 726#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C 727 728#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0 729 730#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8 731 732#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0 733 734#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4 735 736#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8 737 738#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC 739 740#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0 741 742#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4 743 744#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8 745 746#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC 747 748#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0 749 750#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4 751 752#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8 753 754#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC 755 756#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0 757 758#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4 759 760#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8 761 762#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC 763 764#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0 765 766#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4 767 768#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8 769 770#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC 771 772#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00 773 774#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04 775 776#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08 777 778#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C 779 780#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10 781 782#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14 783 784#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18 785 786#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C 787 788#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20 789 790#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24 791 792#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28 793 794#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C 795 796#define mmDMA5_QM_CGM_CFG 0x5A8C70 797 798#define mmDMA5_QM_CGM_STS 0x5A8C74 799 800#define mmDMA5_QM_CGM_CFG1 0x5A8C78 801 802#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80 803 804#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84 805 806#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90 807 808#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94 809 810#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98 811 812#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C 813 814#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0 815 816#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4 817 818#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0 819 820#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4 821 822#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8 823 824#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC 825 826#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0 827 828#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4 829 830#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8 831 832#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00 833 834#endif /* ASIC_REG_DMA5_QM_REGS_H_ */ 835