1/*
2 * Kernel virtual memory layout definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License.  See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2016 Cadence Design Systems Inc.
9 */
10
11#ifndef _XTENSA_KMEM_LAYOUT_H
12#define _XTENSA_KMEM_LAYOUT_H
13
14#include <asm/core.h>
15#include <asm/types.h>
16
17#ifdef CONFIG_MMU
18
19/*
20 * Fixed TLB translations in the processor.
21 */
22
23#define XCHAL_PAGE_TABLE_VADDR	__XTENSA_UL_CONST(0x80000000)
24#define XCHAL_PAGE_TABLE_SIZE	__XTENSA_UL_CONST(0x00400000)
25
26#if defined(CONFIG_XTENSA_KSEG_MMU_V2)
27
28#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xd0000000)
29#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xd8000000)
30#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x08000000)
31#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x08000000)
32#define XCHAL_KSEG_TLB_WAY	5
33#define XCHAL_KIO_TLB_WAY	6
34
35#elif defined(CONFIG_XTENSA_KSEG_256M)
36
37#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xb0000000)
38#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)
39#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x10000000)
40#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)
41#define XCHAL_KSEG_TLB_WAY	6
42#define XCHAL_KIO_TLB_WAY	6
43
44#elif defined(CONFIG_XTENSA_KSEG_512M)
45
46#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xa0000000)
47#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)
48#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x20000000)
49#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)
50#define XCHAL_KSEG_TLB_WAY	6
51#define XCHAL_KIO_TLB_WAY	6
52
53#else
54#error Unsupported KSEG configuration
55#endif
56
57#ifdef CONFIG_KSEG_PADDR
58#define XCHAL_KSEG_PADDR        __XTENSA_UL_CONST(CONFIG_KSEG_PADDR)
59#else
60#define XCHAL_KSEG_PADDR	__XTENSA_UL_CONST(0x00000000)
61#endif
62
63#if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1)
64#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
65#endif
66
67#endif
68
69/* KIO definition */
70
71#if XCHAL_HAVE_PTP_MMU
72#define XCHAL_KIO_CACHED_VADDR		0xe0000000
73#define XCHAL_KIO_BYPASS_VADDR		0xf0000000
74#define XCHAL_KIO_DEFAULT_PADDR		0xf0000000
75#else
76#define XCHAL_KIO_BYPASS_VADDR		XCHAL_KIO_PADDR
77#define XCHAL_KIO_DEFAULT_PADDR		0x90000000
78#endif
79#define XCHAL_KIO_SIZE			0x10000000
80
81#if (!XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY) && defined(CONFIG_USE_OF)
82#define XCHAL_KIO_PADDR			xtensa_get_kio_paddr()
83#ifndef __ASSEMBLY__
84extern unsigned long xtensa_kio_paddr;
85
86static inline unsigned long xtensa_get_kio_paddr(void)
87{
88	return xtensa_kio_paddr;
89}
90#endif
91#else
92#define XCHAL_KIO_PADDR			XCHAL_KIO_DEFAULT_PADDR
93#endif
94
95/* KERNEL_STACK definition */
96
97#ifndef CONFIG_KASAN
98#define KERNEL_STACK_SHIFT	13
99#else
100#define KERNEL_STACK_SHIFT	15
101#endif
102#define KERNEL_STACK_SIZE	(1 << KERNEL_STACK_SHIFT)
103
104#endif
105