1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2004 Konrad Eisele (eiselekd@web.de,konrad@gaisler.com) Gaisler Research 4 * Copyright (C) 2004 Stefan Holst (mail@s-holst.de) Uni-Stuttgart 5 * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB 6 * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB 7 */ 8 9#ifndef LEON_H_INCLUDE 10#define LEON_H_INCLUDE 11 12/* mmu register access, ASI_LEON_MMUREGS */ 13#define LEON_CNR_CTRL 0x000 14#define LEON_CNR_CTXP 0x100 15#define LEON_CNR_CTX 0x200 16#define LEON_CNR_F 0x300 17#define LEON_CNR_FADDR 0x400 18 19#define LEON_CNR_CTX_NCTX 256 /*number of MMU ctx */ 20 21#define LEON_CNR_CTRL_TLBDIS 0x80000000 22 23#define LEON_MMUTLB_ENT_MAX 64 24 25/* 26 * diagnostic access from mmutlb.vhd: 27 * 0: pte address 28 * 4: pte 29 * 8: additional flags 30 */ 31#define LEON_DIAGF_LVL 0x3 32#define LEON_DIAGF_WR 0x8 33#define LEON_DIAGF_WR_SHIFT 3 34#define LEON_DIAGF_HIT 0x10 35#define LEON_DIAGF_HIT_SHIFT 4 36#define LEON_DIAGF_CTX 0x1fe0 37#define LEON_DIAGF_CTX_SHIFT 5 38#define LEON_DIAGF_VALID 0x2000 39#define LEON_DIAGF_VALID_SHIFT 13 40 41/* irq masks */ 42#define LEON_HARD_INT(x) (1 << (x)) /* irq 0-15 */ 43#define LEON_IRQMASK_R 0x0000fffe /* bit 15- 1 of lregs.irqmask */ 44#define LEON_IRQPRIO_R 0xfffe0000 /* bit 31-17 of lregs.irqmask */ 45 46#define LEON_MCFG2_SRAMDIS 0x00002000 47#define LEON_MCFG2_SDRAMEN 0x00004000 48#define LEON_MCFG2_SRAMBANKSZ 0x00001e00 /* [12-9] */ 49#define LEON_MCFG2_SRAMBANKSZ_SHIFT 9 50#define LEON_MCFG2_SDRAMBANKSZ 0x03800000 /* [25-23] */ 51#define LEON_MCFG2_SDRAMBANKSZ_SHIFT 23 52 53#define LEON_TCNT0_MASK 0x7fffff 54 55 56#define ASI_LEON3_SYSCTRL 0x02 57#define ASI_LEON3_SYSCTRL_ICFG 0x08 58#define ASI_LEON3_SYSCTRL_DCFG 0x0c 59#define ASI_LEON3_SYSCTRL_CFG_SNOOPING (1 << 27) 60#define ASI_LEON3_SYSCTRL_CFG_SSIZE(c) (1 << ((c >> 20) & 0xf)) 61 62#ifndef __ASSEMBLY__ 63 64/* do a physical address bypass write, i.e. for 0x80000000 */ 65static inline void leon_store_reg(unsigned long paddr, unsigned long value) 66{ 67 __asm__ __volatile__("sta %0, [%1] %2\n\t" : : "r"(value), "r"(paddr), 68 "i"(ASI_LEON_BYPASS) : "memory"); 69} 70 71/* do a physical address bypass load, i.e. for 0x80000000 */ 72static inline unsigned long leon_load_reg(unsigned long paddr) 73{ 74 unsigned long retval; 75 __asm__ __volatile__("lda [%1] %2, %0\n\t" : 76 "=r"(retval) : "r"(paddr), "i"(ASI_LEON_BYPASS)); 77 return retval; 78} 79 80/* macro access for leon_load_reg() and leon_store_reg() */ 81#define LEON3_BYPASS_LOAD_PA(x) (leon_load_reg((unsigned long)(x))) 82#define LEON3_BYPASS_STORE_PA(x, v) (leon_store_reg((unsigned long)(x), (unsigned long)(v))) 83#define LEON_BYPASS_LOAD_PA(x) leon_load_reg((unsigned long)(x)) 84#define LEON_BYPASS_STORE_PA(x, v) leon_store_reg((unsigned long)(x), (unsigned long)(v)) 85 86void leon_switch_mm(void); 87void leon_init_IRQ(void); 88 89static inline unsigned long sparc_leon3_get_dcachecfg(void) 90{ 91 unsigned int retval; 92 __asm__ __volatile__("lda [%1] %2, %0\n\t" : 93 "=r"(retval) : 94 "r"(ASI_LEON3_SYSCTRL_DCFG), 95 "i"(ASI_LEON3_SYSCTRL)); 96 return retval; 97} 98 99/* enable snooping */ 100static inline void sparc_leon3_enable_snooping(void) 101{ 102 __asm__ __volatile__ ("lda [%%g0] 2, %%l1\n\t" 103 "set 0x800000, %%l2\n\t" 104 "or %%l2, %%l1, %%l2\n\t" 105 "sta %%l2, [%%g0] 2\n\t" : : : "l1", "l2"); 106}; 107 108static inline int sparc_leon3_snooping_enabled(void) 109{ 110 u32 cctrl; 111 __asm__ __volatile__("lda [%%g0] 2, %0\n\t" : "=r"(cctrl)); 112 return ((cctrl >> 23) & 1) && ((cctrl >> 17) & 1); 113}; 114 115static inline void sparc_leon3_disable_cache(void) 116{ 117 __asm__ __volatile__ ("lda [%%g0] 2, %%l1\n\t" 118 "set 0x00000f, %%l2\n\t" 119 "andn %%l2, %%l1, %%l2\n\t" 120 "sta %%l2, [%%g0] 2\n\t" : : : "l1", "l2"); 121}; 122 123static inline unsigned long sparc_leon3_asr17(void) 124{ 125 u32 asr17; 126 __asm__ __volatile__ ("rd %%asr17, %0\n\t" : "=r"(asr17)); 127 return asr17; 128}; 129 130static inline int sparc_leon3_cpuid(void) 131{ 132 return sparc_leon3_asr17() >> 28; 133} 134 135#endif /*!__ASSEMBLY__*/ 136 137#ifdef CONFIG_SMP 138# define LEON3_IRQ_IPI_DEFAULT 13 139# define LEON3_IRQ_TICKER (leon3_gptimer_irq) 140# define LEON3_IRQ_CROSS_CALL 15 141#endif 142 143#if defined(PAGE_SIZE_LEON_8K) 144#define LEON_PAGE_SIZE_LEON 1 145#elif defined(PAGE_SIZE_LEON_16K) 146#define LEON_PAGE_SIZE_LEON 2) 147#else 148#define LEON_PAGE_SIZE_LEON 0 149#endif 150 151#if LEON_PAGE_SIZE_LEON == 0 152/* [ 8, 6, 6 ] + 12 */ 153#define LEON_PGD_SH 24 154#define LEON_PGD_M 0xff 155#define LEON_PMD_SH 18 156#define LEON_PMD_SH_V (LEON_PGD_SH-2) 157#define LEON_PMD_M 0x3f 158#define LEON_PTE_SH 12 159#define LEON_PTE_M 0x3f 160#elif LEON_PAGE_SIZE_LEON == 1 161/* [ 7, 6, 6 ] + 13 */ 162#define LEON_PGD_SH 25 163#define LEON_PGD_M 0x7f 164#define LEON_PMD_SH 19 165#define LEON_PMD_SH_V (LEON_PGD_SH-1) 166#define LEON_PMD_M 0x3f 167#define LEON_PTE_SH 13 168#define LEON_PTE_M 0x3f 169#elif LEON_PAGE_SIZE_LEON == 2 170/* [ 6, 6, 6 ] + 14 */ 171#define LEON_PGD_SH 26 172#define LEON_PGD_M 0x3f 173#define LEON_PMD_SH 20 174#define LEON_PMD_SH_V (LEON_PGD_SH-0) 175#define LEON_PMD_M 0x3f 176#define LEON_PTE_SH 14 177#define LEON_PTE_M 0x3f 178#elif LEON_PAGE_SIZE_LEON == 3 179/* [ 4, 7, 6 ] + 15 */ 180#define LEON_PGD_SH 28 181#define LEON_PGD_M 0x0f 182#define LEON_PMD_SH 21 183#define LEON_PMD_SH_V (LEON_PGD_SH-0) 184#define LEON_PMD_M 0x7f 185#define LEON_PTE_SH 15 186#define LEON_PTE_M 0x3f 187#else 188#error cannot determine LEON_PAGE_SIZE_LEON 189#endif 190 191#define LEON3_XCCR_SETS_MASK 0x07000000UL 192#define LEON3_XCCR_SSIZE_MASK 0x00f00000UL 193 194#define LEON2_CCR_DSETS_MASK 0x03000000UL 195#define LEON2_CFG_SSIZE_MASK 0x00007000UL 196 197#ifndef __ASSEMBLY__ 198struct vm_area_struct; 199 200unsigned long leon_swprobe(unsigned long vaddr, unsigned long *paddr); 201void leon_flush_icache_all(void); 202void leon_flush_dcache_all(void); 203void leon_flush_cache_all(void); 204void leon_flush_tlb_all(void); 205extern int leon_flush_during_switch; 206int leon_flush_needed(void); 207void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page); 208 209/* struct that hold LEON3 cache configuration registers */ 210struct leon3_cacheregs { 211 unsigned long ccr; /* 0x00 - Cache Control Register */ 212 unsigned long iccr; /* 0x08 - Instruction Cache Configuration Register */ 213 unsigned long dccr; /* 0x0c - Data Cache Configuration Register */ 214}; 215 216#include <linux/irq.h> 217#include <linux/interrupt.h> 218 219struct device_node; 220struct task_struct; 221unsigned int leon_build_device_irq(unsigned int real_irq, 222 irq_flow_handler_t flow_handler, 223 const char *name, int do_ack); 224void leon_update_virq_handling(unsigned int virq, 225 irq_flow_handler_t flow_handler, 226 const char *name, int do_ack); 227void leon_init_timers(void); 228void leon_node_init(struct device_node *dp, struct device_node ***nextp); 229void init_leon(void); 230void poke_leonsparc(void); 231void leon3_getCacheRegs(struct leon3_cacheregs *regs); 232extern int leon3_ticker_irq; 233 234#ifdef CONFIG_SMP 235int leon_smp_nrcpus(void); 236void leon_clear_profile_irq(int cpu); 237void leon_smp_done(void); 238void leon_boot_cpus(void); 239int leon_boot_one_cpu(int i, struct task_struct *); 240void leon_init_smp(void); 241void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu); 242irqreturn_t leon_percpu_timer_interrupt(int irq, void *unused); 243 244extern unsigned int smpleon_ipi[]; 245extern unsigned int linux_trap_ipi15_leon[]; 246extern int leon_ipi_irq; 247 248#endif /* CONFIG_SMP */ 249 250#endif /* __ASSEMBLY__ */ 251 252/* macros used in leon_mm.c */ 253#define PFN(x) ((x) >> PAGE_SHIFT) 254#define _pfn_valid(pfn) ((pfn < last_valid_pfn) && (pfn >= PFN(phys_base))) 255#define _SRMMU_PTE_PMASK_LEON 0xffffffff 256 257/* 258 * On LEON PCI Memory space is mapped 1:1 with physical address space. 259 * 260 * I/O space is located at low 64Kbytes in PCI I/O space. The I/O addresses 261 * are converted into CPU addresses to virtual addresses that are mapped with 262 * MMU to the PCI Host PCI I/O space window which are translated to the low 263 * 64Kbytes by the Host controller. 264 */ 265 266#endif 267