1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SH7343 Setup 4 * 5 * Copyright (C) 2006 Paul Mundt 6 */ 7#include <linux/platform_device.h> 8#include <linux/init.h> 9#include <linux/serial.h> 10#include <linux/serial_sci.h> 11#include <linux/uio_driver.h> 12#include <linux/sh_timer.h> 13#include <linux/sh_intc.h> 14#include <asm/clock.h> 15#include <asm/platform_early.h> 16 17/* Serial */ 18static struct plat_sci_port scif0_platform_data = { 19 .scscr = SCSCR_CKE1, 20 .type = PORT_SCIF, 21}; 22 23static struct resource scif0_resources[] = { 24 DEFINE_RES_MEM(0xffe00000, 0x100), 25 DEFINE_RES_IRQ(evt2irq(0xc00)), 26}; 27 28static struct platform_device scif0_device = { 29 .name = "sh-sci", 30 .id = 0, 31 .resource = scif0_resources, 32 .num_resources = ARRAY_SIZE(scif0_resources), 33 .dev = { 34 .platform_data = &scif0_platform_data, 35 }, 36}; 37 38static struct plat_sci_port scif1_platform_data = { 39 .scscr = SCSCR_CKE1, 40 .type = PORT_SCIF, 41}; 42 43static struct resource scif1_resources[] = { 44 DEFINE_RES_MEM(0xffe10000, 0x100), 45 DEFINE_RES_IRQ(evt2irq(0xc20)), 46}; 47 48static struct platform_device scif1_device = { 49 .name = "sh-sci", 50 .id = 1, 51 .resource = scif1_resources, 52 .num_resources = ARRAY_SIZE(scif1_resources), 53 .dev = { 54 .platform_data = &scif1_platform_data, 55 }, 56}; 57 58static struct plat_sci_port scif2_platform_data = { 59 .scscr = SCSCR_CKE1, 60 .type = PORT_SCIF, 61}; 62 63static struct resource scif2_resources[] = { 64 DEFINE_RES_MEM(0xffe20000, 0x100), 65 DEFINE_RES_IRQ(evt2irq(0xc40)), 66}; 67 68static struct platform_device scif2_device = { 69 .name = "sh-sci", 70 .id = 2, 71 .resource = scif2_resources, 72 .num_resources = ARRAY_SIZE(scif2_resources), 73 .dev = { 74 .platform_data = &scif2_platform_data, 75 }, 76}; 77 78static struct plat_sci_port scif3_platform_data = { 79 .scscr = SCSCR_CKE1, 80 .type = PORT_SCIF, 81}; 82 83static struct resource scif3_resources[] = { 84 DEFINE_RES_MEM(0xffe30000, 0x100), 85 DEFINE_RES_IRQ(evt2irq(0xc60)), 86}; 87 88static struct platform_device scif3_device = { 89 .name = "sh-sci", 90 .id = 3, 91 .resource = scif3_resources, 92 .num_resources = ARRAY_SIZE(scif3_resources), 93 .dev = { 94 .platform_data = &scif3_platform_data, 95 }, 96}; 97 98static struct resource iic0_resources[] = { 99 [0] = { 100 .name = "IIC0", 101 .start = 0x04470000, 102 .end = 0x04470017, 103 .flags = IORESOURCE_MEM, 104 }, 105 [1] = { 106 .start = evt2irq(0xe00), 107 .end = evt2irq(0xe60), 108 .flags = IORESOURCE_IRQ, 109 }, 110}; 111 112static struct platform_device iic0_device = { 113 .name = "i2c-sh_mobile", 114 .id = 0, /* "i2c0" clock */ 115 .num_resources = ARRAY_SIZE(iic0_resources), 116 .resource = iic0_resources, 117}; 118 119static struct resource iic1_resources[] = { 120 [0] = { 121 .name = "IIC1", 122 .start = 0x04750000, 123 .end = 0x04750017, 124 .flags = IORESOURCE_MEM, 125 }, 126 [1] = { 127 .start = evt2irq(0x780), 128 .end = evt2irq(0x7e0), 129 .flags = IORESOURCE_IRQ, 130 }, 131}; 132 133static struct platform_device iic1_device = { 134 .name = "i2c-sh_mobile", 135 .id = 1, /* "i2c1" clock */ 136 .num_resources = ARRAY_SIZE(iic1_resources), 137 .resource = iic1_resources, 138}; 139 140static struct uio_info vpu_platform_data = { 141 .name = "VPU4", 142 .version = "0", 143 .irq = evt2irq(0x980), 144}; 145 146static struct resource vpu_resources[] = { 147 [0] = { 148 .name = "VPU", 149 .start = 0xfe900000, 150 .end = 0xfe9022eb, 151 .flags = IORESOURCE_MEM, 152 }, 153 [1] = { 154 /* place holder for contiguous memory */ 155 }, 156}; 157 158static struct platform_device vpu_device = { 159 .name = "uio_pdrv_genirq", 160 .id = 0, 161 .dev = { 162 .platform_data = &vpu_platform_data, 163 }, 164 .resource = vpu_resources, 165 .num_resources = ARRAY_SIZE(vpu_resources), 166}; 167 168static struct uio_info veu_platform_data = { 169 .name = "VEU", 170 .version = "0", 171 .irq = evt2irq(0x8c0), 172}; 173 174static struct resource veu_resources[] = { 175 [0] = { 176 .name = "VEU", 177 .start = 0xfe920000, 178 .end = 0xfe9200b7, 179 .flags = IORESOURCE_MEM, 180 }, 181 [1] = { 182 /* place holder for contiguous memory */ 183 }, 184}; 185 186static struct platform_device veu_device = { 187 .name = "uio_pdrv_genirq", 188 .id = 1, 189 .dev = { 190 .platform_data = &veu_platform_data, 191 }, 192 .resource = veu_resources, 193 .num_resources = ARRAY_SIZE(veu_resources), 194}; 195 196static struct uio_info jpu_platform_data = { 197 .name = "JPU", 198 .version = "0", 199 .irq = evt2irq(0x560), 200}; 201 202static struct resource jpu_resources[] = { 203 [0] = { 204 .name = "JPU", 205 .start = 0xfea00000, 206 .end = 0xfea102d3, 207 .flags = IORESOURCE_MEM, 208 }, 209 [1] = { 210 /* place holder for contiguous memory */ 211 }, 212}; 213 214static struct platform_device jpu_device = { 215 .name = "uio_pdrv_genirq", 216 .id = 2, 217 .dev = { 218 .platform_data = &jpu_platform_data, 219 }, 220 .resource = jpu_resources, 221 .num_resources = ARRAY_SIZE(jpu_resources), 222}; 223 224static struct sh_timer_config cmt_platform_data = { 225 .channels_mask = 0x20, 226}; 227 228static struct resource cmt_resources[] = { 229 DEFINE_RES_MEM(0x044a0000, 0x70), 230 DEFINE_RES_IRQ(evt2irq(0xf00)), 231}; 232 233static struct platform_device cmt_device = { 234 .name = "sh-cmt-32", 235 .id = 0, 236 .dev = { 237 .platform_data = &cmt_platform_data, 238 }, 239 .resource = cmt_resources, 240 .num_resources = ARRAY_SIZE(cmt_resources), 241}; 242 243static struct sh_timer_config tmu0_platform_data = { 244 .channels_mask = 7, 245}; 246 247static struct resource tmu0_resources[] = { 248 DEFINE_RES_MEM(0xffd80000, 0x2c), 249 DEFINE_RES_IRQ(evt2irq(0x400)), 250 DEFINE_RES_IRQ(evt2irq(0x420)), 251 DEFINE_RES_IRQ(evt2irq(0x440)), 252}; 253 254static struct platform_device tmu0_device = { 255 .name = "sh-tmu", 256 .id = 0, 257 .dev = { 258 .platform_data = &tmu0_platform_data, 259 }, 260 .resource = tmu0_resources, 261 .num_resources = ARRAY_SIZE(tmu0_resources), 262}; 263 264static struct platform_device *sh7343_devices[] __initdata = { 265 &scif0_device, 266 &scif1_device, 267 &scif2_device, 268 &scif3_device, 269 &cmt_device, 270 &tmu0_device, 271 &iic0_device, 272 &iic1_device, 273 &vpu_device, 274 &veu_device, 275 &jpu_device, 276}; 277 278static int __init sh7343_devices_setup(void) 279{ 280 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 281 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 282 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 283 284 return platform_add_devices(sh7343_devices, 285 ARRAY_SIZE(sh7343_devices)); 286} 287arch_initcall(sh7343_devices_setup); 288 289static struct platform_device *sh7343_early_devices[] __initdata = { 290 &scif0_device, 291 &scif1_device, 292 &scif2_device, 293 &scif3_device, 294 &cmt_device, 295 &tmu0_device, 296}; 297 298void __init plat_early_device_setup(void) 299{ 300 sh_early_platform_add_devices(sh7343_early_devices, 301 ARRAY_SIZE(sh7343_early_devices)); 302} 303 304enum { 305 UNUSED = 0, 306 ENABLED, 307 DISABLED, 308 309 /* interrupt sources */ 310 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 311 DMAC0, DMAC1, DMAC2, DMAC3, 312 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 313 MFI, VPU, TPU, Z3D4, USBI0, USBI1, 314 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, 315 DMAC4, DMAC5, DMAC_DADERR, 316 KEYSC, 317 SCIF, SCIF1, SCIF2, SCIF3, 318 SIOF0, SIOF1, SIO, 319 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 320 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 321 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 322 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 323 IRDA, SDHI, CMT, TSIF, SIU, 324 TMU0, TMU1, TMU2, 325 JPU, LCDC, 326 327 /* interrupt groups */ 328 329 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB, 330}; 331 332static struct intc_vect vectors[] __initdata = { 333 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 334 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 335 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 336 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 337 INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), 338 INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), 339 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 340 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 341 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 342 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 343 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), 344 INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), 345 INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), 346 INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), 347 INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), 348 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 349 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 350 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), 351 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), 352 INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), 353 INTC_VECT(SIO, 0xd00), 354 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 355 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 356 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 357 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 358 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 359 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 360 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 361 INTC_VECT(SIU, 0xf80), 362 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 363 INTC_VECT(TMU2, 0x440), 364 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 365}; 366 367static struct intc_group groups[] __initdata = { 368 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 369 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 370 INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), 371 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 372 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 373 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 374 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 375 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 376 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 377 INTC_GROUP(USB, USBI0, USBI1), 378}; 379 380static struct intc_mask_reg mask_registers[] __initdata = { 381 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 382 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 383 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 384 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 385 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 386 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 387 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 388 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 389 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 390 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, 391 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 392 { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, 393 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 394 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 395 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 396 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 397 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } }, 398 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 399 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 400 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 401 { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, 402 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 403 { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, 404 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 405 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 406}; 407 408static struct intc_prio_reg prio_registers[] __initdata = { 409 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 410 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 411 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 412 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 413 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, 414 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, 415 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, 416 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, 417 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 418 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, 419 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 420 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 421}; 422 423static struct intc_sense_reg sense_registers[] __initdata = { 424 { 0xa414001c, 16, 2, /* ICR1 */ 425 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 426}; 427 428static struct intc_mask_reg ack_registers[] __initdata = { 429 { 0xa4140024, 0, 8, /* INTREQ00 */ 430 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 431}; 432 433static struct intc_desc intc_desc __initdata = { 434 .name = "sh7343", 435 .force_enable = ENABLED, 436 .force_disable = DISABLED, 437 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 438 prio_registers, sense_registers, ack_registers), 439}; 440 441void __init plat_irq_setup(void) 442{ 443 register_intc_controller(&intc_desc); 444} 445