1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7760 Setup
4 *
5 *  Copyright (C) 2006  Paul Mundt
6 */
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/serial.h>
10#include <linux/sh_timer.h>
11#include <linux/sh_intc.h>
12#include <linux/serial_sci.h>
13#include <linux/io.h>
14#include <asm/platform_early.h>
15
16enum {
17	UNUSED = 0,
18
19	/* interrupt sources */
20	IRL0, IRL1, IRL2, IRL3,
21	HUDI, GPIOI, DMAC,
22	IRQ4, IRQ5, IRQ6, IRQ7,
23	HCAN20, HCAN21,
24	SSI0, SSI1,
25	HAC0, HAC1,
26	I2C0, I2C1,
27	USB, LCDC,
28	DMABRG0, DMABRG1, DMABRG2,
29	SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
30	SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
31	SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
32	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
33	HSPI,
34	MMCIF0, MMCIF1, MMCIF2, MMCIF3,
35	MFI, ADC, CMT,
36	TMU0, TMU1, TMU2,
37	WDT, REF,
38
39	/* interrupt groups */
40	DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
41};
42
43static struct intc_vect vectors[] __initdata = {
44	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49	INTC_VECT(DMAC, 0x6c0),
50	INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51	INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52	INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
53	INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
54	INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
55	INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
56	INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
57	INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
58	INTC_VECT(DMABRG2, 0xac0),
59	INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
60	INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
61	INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
62	INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
63	INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
64	INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
65	INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
66	INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
67	INTC_VECT(HSPI, 0xc80),
68	INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
69	INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
70	INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
71	INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
72	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
73	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
74	INTC_VECT(WDT, 0x560),
75	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
76};
77
78static struct intc_group groups[] __initdata = {
79	INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
80	INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
81	INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
82	INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
83	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
84	INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
85};
86
87static struct intc_mask_reg mask_registers[] __initdata = {
88	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
89	  { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
90	    SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
91	    0, DMABRG0, DMABRG1, DMABRG2,
92	    SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
93	    SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
94	    SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
95	{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
96	  { 0, 0, 0, 0, 0, 0, 0, 0,
97	    SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
98	    HSPI, MMCIF0, MMCIF1, MMCIF2,
99	    MMCIF3, 0, 0, 0, 0, 0, 0, 0,
100	    0, MFI, 0, 0, 0, 0, ADC, CMT, } },
101};
102
103static struct intc_prio_reg prio_registers[] __initdata = {
104	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
105	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
106	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
107	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
108	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
109	{ 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
110						 HAC0, HAC1, I2C0, I2C1 } },
111	{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
112						 SCIF1, SCIF2, SIM, HSPI } },
113	{ 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
114						 MFI, 0, ADC, CMT } },
115};
116
117static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
118			 mask_registers, prio_registers, NULL);
119
120static struct intc_vect vectors_irq[] __initdata = {
121	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
122	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
123};
124
125static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
126			 mask_registers, prio_registers, NULL);
127
128static struct plat_sci_port scif0_platform_data = {
129	.scscr		= SCSCR_REIE,
130	.type		= PORT_SCIF,
131	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
132};
133
134static struct resource scif0_resources[] = {
135	DEFINE_RES_MEM(0xfe600000, 0x100),
136	DEFINE_RES_IRQ(evt2irq(0x880)),
137	DEFINE_RES_IRQ(evt2irq(0x8a0)),
138	DEFINE_RES_IRQ(evt2irq(0x8e0)),
139	DEFINE_RES_IRQ(evt2irq(0x8c0)),
140};
141
142static struct platform_device scif0_device = {
143	.name		= "sh-sci",
144	.id		= 0,
145	.resource	= scif0_resources,
146	.num_resources	= ARRAY_SIZE(scif0_resources),
147	.dev		= {
148		.platform_data	= &scif0_platform_data,
149	},
150};
151
152static struct plat_sci_port scif1_platform_data = {
153	.type		= PORT_SCIF,
154	.scscr		= SCSCR_REIE,
155	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
156};
157
158static struct resource scif1_resources[] = {
159	DEFINE_RES_MEM(0xfe610000, 0x100),
160	DEFINE_RES_IRQ(evt2irq(0xb00)),
161	DEFINE_RES_IRQ(evt2irq(0xb20)),
162	DEFINE_RES_IRQ(evt2irq(0xb60)),
163	DEFINE_RES_IRQ(evt2irq(0xb40)),
164};
165
166static struct platform_device scif1_device = {
167	.name		= "sh-sci",
168	.id		= 1,
169	.resource	= scif1_resources,
170	.num_resources	= ARRAY_SIZE(scif1_resources),
171	.dev		= {
172		.platform_data	= &scif1_platform_data,
173	},
174};
175
176static struct plat_sci_port scif2_platform_data = {
177	.scscr		= SCSCR_REIE,
178	.type		= PORT_SCIF,
179	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
180};
181
182static struct resource scif2_resources[] = {
183	DEFINE_RES_MEM(0xfe620000, 0x100),
184	DEFINE_RES_IRQ(evt2irq(0xb80)),
185	DEFINE_RES_IRQ(evt2irq(0xba0)),
186	DEFINE_RES_IRQ(evt2irq(0xbe0)),
187	DEFINE_RES_IRQ(evt2irq(0xbc0)),
188};
189
190static struct platform_device scif2_device = {
191	.name		= "sh-sci",
192	.id		= 2,
193	.resource	= scif2_resources,
194	.num_resources	= ARRAY_SIZE(scif2_resources),
195	.dev		= {
196		.platform_data	= &scif2_platform_data,
197	},
198};
199
200static struct plat_sci_port scif3_platform_data = {
201	/*
202	 * This is actually a SIM card module serial port, based on an SCI with
203	 * additional registers. The sh-sci driver doesn't support the SIM port
204	 * type, declare it as a SCI. Don't declare the additional registers in
205	 * the memory resource or the driver will compute an incorrect regshift
206	 * value.
207	 */
208	.type		= PORT_SCI,
209};
210
211static struct resource scif3_resources[] = {
212	DEFINE_RES_MEM(0xfe480000, 0x10),
213	DEFINE_RES_IRQ(evt2irq(0xc00)),
214	DEFINE_RES_IRQ(evt2irq(0xc20)),
215	DEFINE_RES_IRQ(evt2irq(0xc40)),
216};
217
218static struct platform_device scif3_device = {
219	.name		= "sh-sci",
220	.id		= 3,
221	.resource	= scif3_resources,
222	.num_resources	= ARRAY_SIZE(scif3_resources),
223	.dev		= {
224		.platform_data	= &scif3_platform_data,
225	},
226};
227
228static struct sh_timer_config tmu0_platform_data = {
229	.channels_mask = 7,
230};
231
232static struct resource tmu0_resources[] = {
233	DEFINE_RES_MEM(0xffd80000, 0x30),
234	DEFINE_RES_IRQ(evt2irq(0x400)),
235	DEFINE_RES_IRQ(evt2irq(0x420)),
236	DEFINE_RES_IRQ(evt2irq(0x440)),
237};
238
239static struct platform_device tmu0_device = {
240	.name		= "sh-tmu",
241	.id		= 0,
242	.dev = {
243		.platform_data	= &tmu0_platform_data,
244	},
245	.resource	= tmu0_resources,
246	.num_resources	= ARRAY_SIZE(tmu0_resources),
247};
248
249
250static struct platform_device *sh7760_devices[] __initdata = {
251	&scif0_device,
252	&scif1_device,
253	&scif2_device,
254	&scif3_device,
255	&tmu0_device,
256};
257
258static int __init sh7760_devices_setup(void)
259{
260	return platform_add_devices(sh7760_devices,
261				    ARRAY_SIZE(sh7760_devices));
262}
263arch_initcall(sh7760_devices_setup);
264
265static struct platform_device *sh7760_early_devices[] __initdata = {
266	&scif0_device,
267	&scif1_device,
268	&scif2_device,
269	&scif3_device,
270	&tmu0_device,
271};
272
273void __init plat_early_device_setup(void)
274{
275	sh_early_platform_add_devices(sh7760_early_devices,
276				   ARRAY_SIZE(sh7760_early_devices));
277}
278
279#define INTC_ICR	0xffd00000UL
280#define INTC_ICR_IRLM	(1 << 7)
281
282void __init plat_irq_setup_pins(int mode)
283{
284	switch (mode) {
285	case IRQ_MODE_IRQ:
286		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
287		register_intc_controller(&intc_desc_irq);
288		break;
289	default:
290		BUG();
291	}
292}
293
294void __init plat_irq_setup(void)
295{
296	register_intc_controller(&intc_desc);
297}
298