1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas Technology Corp. R0P7785LC0011RL Support.
4 *
5 * Copyright (C) 2008  Yoshihiro Shimoda
6 * Copyright (C) 2009  Paul Mundt
7 */
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/sm501.h>
11#include <linux/sm501-regs.h>
12#include <linux/fb.h>
13#include <linux/mtd/physmap.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/i2c.h>
17#include <linux/platform_data/i2c-pca-platform.h>
18#include <linux/i2c-algo-pca.h>
19#include <linux/usb/r8a66597.h>
20#include <linux/sh_intc.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/errno.h>
25#include <linux/gpio/machine.h>
26#include <mach/sh7785lcr.h>
27#include <cpu/sh7785.h>
28#include <asm/heartbeat.h>
29#include <asm/clock.h>
30#include <asm/bl_bit.h>
31
32/*
33 * NOTE: This board has 2 physical memory maps.
34 *	 Please look at include/asm-sh/sh7785lcr.h or hardware manual.
35 */
36static struct resource heartbeat_resource = {
37	.start	= PLD_LEDCR,
38	.end	= PLD_LEDCR,
39	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
40};
41
42static struct platform_device heartbeat_device = {
43	.name		= "heartbeat",
44	.id		= -1,
45	.num_resources	= 1,
46	.resource	= &heartbeat_resource,
47};
48
49static struct mtd_partition nor_flash_partitions[] = {
50	{
51		.name		= "loader",
52		.offset		= 0x00000000,
53		.size		= 512 * 1024,
54	},
55	{
56		.name		= "bootenv",
57		.offset		= MTDPART_OFS_APPEND,
58		.size		= 512 * 1024,
59	},
60	{
61		.name		= "kernel",
62		.offset		= MTDPART_OFS_APPEND,
63		.size		= 4 * 1024 * 1024,
64	},
65	{
66		.name		= "data",
67		.offset		= MTDPART_OFS_APPEND,
68		.size		= MTDPART_SIZ_FULL,
69	},
70};
71
72static struct physmap_flash_data nor_flash_data = {
73	.width		= 4,
74	.parts		= nor_flash_partitions,
75	.nr_parts	= ARRAY_SIZE(nor_flash_partitions),
76};
77
78static struct resource nor_flash_resources[] = {
79	[0]	= {
80		.start	= NOR_FLASH_ADDR,
81		.end	= NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
82		.flags	= IORESOURCE_MEM,
83	}
84};
85
86static struct platform_device nor_flash_device = {
87	.name		= "physmap-flash",
88	.dev		= {
89		.platform_data	= &nor_flash_data,
90	},
91	.num_resources	= ARRAY_SIZE(nor_flash_resources),
92	.resource	= nor_flash_resources,
93};
94
95static struct r8a66597_platdata r8a66597_data = {
96	.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
97	.vif = 1,
98};
99
100static struct resource r8a66597_usb_host_resources[] = {
101	[0] = {
102		.start	= R8A66597_ADDR,
103		.end	= R8A66597_ADDR + R8A66597_SIZE - 1,
104		.flags	= IORESOURCE_MEM,
105	},
106	[1] = {
107		.start	= evt2irq(0x240),
108		.end	= evt2irq(0x240),
109		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
110	},
111};
112
113static struct platform_device r8a66597_usb_host_device = {
114	.name		= "r8a66597_hcd",
115	.id		= -1,
116	.dev = {
117		.dma_mask		= NULL,
118		.coherent_dma_mask	= 0xffffffff,
119		.platform_data		= &r8a66597_data,
120	},
121	.num_resources	= ARRAY_SIZE(r8a66597_usb_host_resources),
122	.resource	= r8a66597_usb_host_resources,
123};
124
125static struct resource sm501_resources[] = {
126	[0]	= {
127		.start	= SM107_MEM_ADDR,
128		.end	= SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
129		.flags	= IORESOURCE_MEM,
130	},
131	[1]	= {
132		.start	= SM107_REG_ADDR,
133		.end	= SM107_REG_ADDR + SM107_REG_SIZE - 1,
134		.flags	= IORESOURCE_MEM,
135	},
136	[2]	= {
137		.start	= evt2irq(0x340),
138		.flags	= IORESOURCE_IRQ,
139	},
140};
141
142static struct fb_videomode sm501_default_mode_crt = {
143	.pixclock	= 35714,	/* 28MHz */
144	.xres		= 640,
145	.yres		= 480,
146	.left_margin	= 105,
147	.right_margin	= 16,
148	.upper_margin	= 33,
149	.lower_margin	= 10,
150	.hsync_len	= 39,
151	.vsync_len	= 2,
152	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
153};
154
155static struct fb_videomode sm501_default_mode_pnl = {
156	.pixclock	= 40000,	/* 25MHz */
157	.xres		= 640,
158	.yres		= 480,
159	.left_margin	= 2,
160	.right_margin	= 16,
161	.upper_margin	= 33,
162	.lower_margin	= 10,
163	.hsync_len	= 39,
164	.vsync_len	= 2,
165	.sync		= 0,
166};
167
168static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
169	.def_bpp	= 16,
170	.def_mode	= &sm501_default_mode_pnl,
171	.flags		= SM501FB_FLAG_USE_INIT_MODE |
172			  SM501FB_FLAG_USE_HWCURSOR |
173			  SM501FB_FLAG_USE_HWACCEL |
174			  SM501FB_FLAG_DISABLE_AT_EXIT |
175			  SM501FB_FLAG_PANEL_NO_VBIASEN,
176};
177
178static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
179	.def_bpp	= 16,
180	.def_mode	= &sm501_default_mode_crt,
181	.flags		= SM501FB_FLAG_USE_INIT_MODE |
182			  SM501FB_FLAG_USE_HWCURSOR |
183			  SM501FB_FLAG_USE_HWACCEL |
184			  SM501FB_FLAG_DISABLE_AT_EXIT,
185};
186
187static struct sm501_platdata_fb sm501_fb_pdata = {
188	.fb_route	= SM501_FB_OWN,
189	.fb_crt		= &sm501_pdata_fbsub_crt,
190	.fb_pnl		= &sm501_pdata_fbsub_pnl,
191};
192
193static struct sm501_initdata sm501_initdata = {
194	.gpio_high	= {
195		.set	= 0x00001fe0,
196		.mask	= 0x0,
197	},
198	.devices	= 0,
199	.mclk		= 84 * 1000000,
200	.m1xclk		= 112 * 1000000,
201};
202
203static struct sm501_platdata sm501_platform_data = {
204	.init		= &sm501_initdata,
205	.fb		= &sm501_fb_pdata,
206};
207
208static struct platform_device sm501_device = {
209	.name		= "sm501",
210	.id		= -1,
211	.dev		= {
212		.platform_data	= &sm501_platform_data,
213	},
214	.num_resources	= ARRAY_SIZE(sm501_resources),
215	.resource	= sm501_resources,
216};
217
218static struct resource i2c_proto_resources[] = {
219	[0] = {
220		.start	= PCA9564_PROTO_32BIT_ADDR,
221		.end	= PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
222		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
223	},
224	[1] = {
225		.start	= evt2irq(0x380),
226		.end	= evt2irq(0x380),
227		.flags	= IORESOURCE_IRQ,
228	},
229};
230
231static struct resource i2c_resources[] = {
232	[0] = {
233		.start	= PCA9564_ADDR,
234		.end	= PCA9564_ADDR + PCA9564_SIZE - 1,
235		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
236	},
237	[1] = {
238		.start	= evt2irq(0x380),
239		.end	= evt2irq(0x380),
240		.flags	= IORESOURCE_IRQ,
241	},
242};
243
244static struct gpiod_lookup_table i2c_gpio_table = {
245	.dev_id = "i2c.0",
246	.table = {
247		GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW),
248		{ },
249	},
250};
251
252static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
253	.i2c_clock_speed	= I2C_PCA_CON_330kHz,
254	.timeout		= HZ,
255};
256
257static struct platform_device i2c_device = {
258	.name		= "i2c-pca-platform",
259	.id		= -1,
260	.dev		= {
261		.platform_data	= &i2c_platform_data,
262	},
263	.num_resources	= ARRAY_SIZE(i2c_resources),
264	.resource	= i2c_resources,
265};
266
267static struct platform_device *sh7785lcr_devices[] __initdata = {
268	&heartbeat_device,
269	&nor_flash_device,
270	&r8a66597_usb_host_device,
271	&sm501_device,
272	&i2c_device,
273};
274
275static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
276	{
277		I2C_BOARD_INFO("r2025sd", 0x32),
278	},
279};
280
281static int __init sh7785lcr_devices_setup(void)
282{
283	i2c_register_board_info(0, sh7785lcr_i2c_devices,
284				ARRAY_SIZE(sh7785lcr_i2c_devices));
285
286	if (mach_is_sh7785lcr_pt()) {
287		i2c_device.resource = i2c_proto_resources;
288		i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
289	}
290
291	gpiod_add_lookup_table(&i2c_gpio_table);
292	return platform_add_devices(sh7785lcr_devices,
293				    ARRAY_SIZE(sh7785lcr_devices));
294}
295device_initcall(sh7785lcr_devices_setup);
296
297/* Initialize IRQ setting */
298static void __init init_sh7785lcr_IRQ(void)
299{
300	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
301	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
302}
303
304static int sh7785lcr_clk_init(void)
305{
306	struct clk *clk;
307	int ret;
308
309	clk = clk_get(NULL, "extal");
310	if (IS_ERR(clk))
311		return PTR_ERR(clk);
312	ret = clk_set_rate(clk, 33333333);
313	clk_put(clk);
314
315	return ret;
316}
317
318static void sh7785lcr_power_off(void)
319{
320	unsigned char *p;
321
322	p = ioremap(PLD_POFCR, PLD_POFCR + 1);
323	if (!p) {
324		printk(KERN_ERR "%s: ioremap error.\n", __func__);
325		return;
326	}
327	*p = 0x01;
328	iounmap(p);
329	set_bl_bit();
330	while (1)
331		cpu_relax();
332}
333
334/* Initialize the board */
335static void __init sh7785lcr_setup(char **cmdline_p)
336{
337	void __iomem *sm501_reg;
338
339	printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
340
341	pm_power_off = sh7785lcr_power_off;
342
343	/* sm501 DRAM configuration */
344	sm501_reg = ioremap(SM107_REG_ADDR, SM501_DRAM_CONTROL);
345	if (!sm501_reg) {
346		printk(KERN_ERR "%s: ioremap error.\n", __func__);
347		return;
348	}
349
350	writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
351	iounmap(sm501_reg);
352}
353
354/* Return the board specific boot mode pin configuration */
355static int sh7785lcr_mode_pins(void)
356{
357	int value = 0;
358
359	/* These are the factory default settings of S1 and S2.
360	 * If you change these dip switches then you will need to
361	 * adjust the values below as well.
362	 */
363	value |= MODE_PIN4; /* Clock Mode 16 */
364	value |= MODE_PIN5; /* 32-bit Area0 bus width */
365	value |= MODE_PIN6; /* 32-bit Area0 bus width */
366	value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
367	value |= MODE_PIN8; /* Little Endian */
368	value |= MODE_PIN9; /* Master Mode */
369	value |= MODE_PIN14; /* No PLL step-up */
370
371	return value;
372}
373
374/*
375 * The Machine Vector
376 */
377static struct sh_machine_vector mv_sh7785lcr __initmv = {
378	.mv_name		= "SH7785LCR",
379	.mv_setup		= sh7785lcr_setup,
380	.mv_clk_init		= sh7785lcr_clk_init,
381	.mv_init_irq		= init_sh7785lcr_IRQ,
382	.mv_mode_pins		= sh7785lcr_mode_pins,
383};
384
385