1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/barrier.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2013 Regents of the University of California
7 * Copyright (C) 2017 SiFive
8 */
9
10#ifndef _ASM_RISCV_BARRIER_H
11#define _ASM_RISCV_BARRIER_H
12
13#ifndef __ASSEMBLY__
14#include <asm/fence.h>
15
16#define nop()		__asm__ __volatile__ ("nop")
17#define __nops(n)	".rept	" #n "\nnop\n.endr\n"
18#define nops(n)		__asm__ __volatile__ (__nops(n))
19
20
21/* These barriers need to enforce ordering on both devices or memory. */
22#define __mb()		RISCV_FENCE(iorw, iorw)
23#define __rmb()		RISCV_FENCE(ir, ir)
24#define __wmb()		RISCV_FENCE(ow, ow)
25
26/* These barriers do not need to enforce ordering on devices, just memory. */
27#define __smp_mb()	RISCV_FENCE(rw, rw)
28#define __smp_rmb()	RISCV_FENCE(r, r)
29#define __smp_wmb()	RISCV_FENCE(w, w)
30
31#define __smp_store_release(p, v)					\
32do {									\
33	compiletime_assert_atomic_type(*p);				\
34	RISCV_FENCE(rw, w);						\
35	WRITE_ONCE(*p, v);						\
36} while (0)
37
38#define __smp_load_acquire(p)						\
39({									\
40	typeof(*p) ___p1 = READ_ONCE(*p);				\
41	compiletime_assert_atomic_type(*p);				\
42	RISCV_FENCE(r, rw);						\
43	___p1;								\
44})
45
46/*
47 * This is a very specific barrier: it's currently only used in two places in
48 * the kernel, both in the scheduler.  See include/linux/spinlock.h for the two
49 * orderings it guarantees, but the "critical section is RCsc" guarantee
50 * mandates a barrier on RISC-V.  The sequence looks like:
51 *
52 *    lr.aq lock
53 *    sc    lock <= LOCKED
54 *    smp_mb__after_spinlock()
55 *    // critical section
56 *    lr    lock
57 *    sc.rl lock <= UNLOCKED
58 *
59 * The AQ/RL pair provides a RCpc critical section, but there's not really any
60 * way we can take advantage of that here because the ordering is only enforced
61 * on that one lock.  Thus, we're just doing a full fence.
62 *
63 * Since we allow writeX to be called from preemptive regions we need at least
64 * an "o" in the predecessor set to ensure device writes are visible before the
65 * task is marked as available for scheduling on a new hart.  While I don't see
66 * any concrete reason we need a full IO fence, it seems safer to just upgrade
67 * this in order to avoid any IO crossing a scheduling boundary.  In both
68 * instances the scheduler pairs this with an mb(), so nothing is necessary on
69 * the new hart.
70 */
71#define smp_mb__after_spinlock()	RISCV_FENCE(iorw, iorw)
72
73#include <asm-generic/barrier.h>
74
75#endif /* __ASSEMBLY__ */
76
77#endif /* _ASM_RISCV_BARRIER_H */
78