1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This program is used to generate definitions needed by
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach kernel code:
7 * generate asm statements containing #defines,
8 * compile this file to assembler, and then extract the
9 * #defines from the assembly-language output.
10 */
11
12#include <linux/compat.h>
13#include <linux/signal.h>
14#include <linux/sched.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/types.h>
19#include <linux/mman.h>
20#include <linux/mm.h>
21#include <linux/suspend.h>
22#include <linux/hrtimer.h>
23#ifdef CONFIG_PPC64
24#include <linux/time.h>
25#include <linux/hardirq.h>
26#endif
27#include <linux/kbuild.h>
28
29#include <asm/io.h>
30#include <asm/page.h>
31#include <asm/processor.h>
32#include <asm/cputable.h>
33#include <asm/thread_info.h>
34#include <asm/rtas.h>
35#include <asm/vdso_datapage.h>
36#include <asm/dbell.h>
37#ifdef CONFIG_PPC64
38#include <asm/paca.h>
39#include <asm/lppaca.h>
40#include <asm/cache.h>
41#include <asm/mmu.h>
42#include <asm/hvcall.h>
43#include <asm/xics.h>
44#endif
45#ifdef CONFIG_PPC_POWERNV
46#include <asm/opal.h>
47#endif
48#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
49#include <linux/kvm_host.h>
50#endif
51#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
52#include <asm/kvm_book3s.h>
53#include <asm/kvm_ppc.h>
54#endif
55
56#ifdef CONFIG_PPC32
57#ifdef CONFIG_BOOKE_OR_40x
58#include "head_booke.h"
59#endif
60#endif
61
62#if defined(CONFIG_PPC_E500)
63#include "../mm/mmu_decl.h"
64#endif
65
66#ifdef CONFIG_PPC_8xx
67#include <asm/fixmap.h>
68#endif
69
70#ifdef CONFIG_XMON
71#include "../xmon/xmon_bpts.h"
72#endif
73
74#define STACK_PT_REGS_OFFSET(sym, val)	\
75	DEFINE(sym, STACK_INT_FRAME_REGS + offsetof(struct pt_regs, val))
76
77int main(void)
78{
79	OFFSET(THREAD, task_struct, thread);
80	OFFSET(MM, task_struct, mm);
81#ifdef CONFIG_STACKPROTECTOR
82	OFFSET(TASK_CANARY, task_struct, stack_canary);
83#ifdef CONFIG_PPC64
84	OFFSET(PACA_CANARY, paca_struct, canary);
85#endif
86#endif
87#ifdef CONFIG_PPC32
88#ifdef CONFIG_PPC_RTAS
89	OFFSET(RTAS_SP, thread_struct, rtas_sp);
90#endif
91#endif /* CONFIG_PPC64 */
92	OFFSET(TASK_STACK, task_struct, stack);
93#ifdef CONFIG_SMP
94	OFFSET(TASK_CPU, task_struct, thread_info.cpu);
95#endif
96
97#ifdef CONFIG_LIVEPATCH_64
98	OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
99#endif
100
101	OFFSET(KSP, thread_struct, ksp);
102	OFFSET(PT_REGS, thread_struct, regs);
103#ifdef CONFIG_BOOKE
104	OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
105#endif
106#ifdef CONFIG_PPC_FPU
107	OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
108	OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
109	OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
110#endif
111	OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
112	OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
113#ifdef CONFIG_ALTIVEC
114	OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
115	OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
116	OFFSET(THREAD_USED_VR, thread_struct, used_vr);
117	OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
118	OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
119#endif /* CONFIG_ALTIVEC */
120#ifdef CONFIG_VSX
121	OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
122#endif /* CONFIG_VSX */
123#ifdef CONFIG_PPC64
124	OFFSET(KSP_VSID, thread_struct, ksp_vsid);
125#else /* CONFIG_PPC64 */
126	OFFSET(PGDIR, thread_struct, pgdir);
127	OFFSET(SRR0, thread_struct, srr0);
128	OFFSET(SRR1, thread_struct, srr1);
129	OFFSET(DAR, thread_struct, dar);
130	OFFSET(DSISR, thread_struct, dsisr);
131#ifdef CONFIG_PPC_BOOK3S_32
132	OFFSET(THR0, thread_struct, r0);
133	OFFSET(THR3, thread_struct, r3);
134	OFFSET(THR4, thread_struct, r4);
135	OFFSET(THR5, thread_struct, r5);
136	OFFSET(THR6, thread_struct, r6);
137	OFFSET(THR8, thread_struct, r8);
138	OFFSET(THR9, thread_struct, r9);
139	OFFSET(THR11, thread_struct, r11);
140	OFFSET(THLR, thread_struct, lr);
141	OFFSET(THCTR, thread_struct, ctr);
142	OFFSET(THSR0, thread_struct, sr0);
143#endif
144#ifdef CONFIG_SPE
145	OFFSET(THREAD_EVR0, thread_struct, evr[0]);
146	OFFSET(THREAD_ACC, thread_struct, acc);
147	OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
148#endif /* CONFIG_SPE */
149#endif /* CONFIG_PPC64 */
150#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
151	OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
152#endif
153#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
154	OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
155#endif
156
157#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
158	OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
159	OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
160	OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
161	OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
162	OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
163	OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
164	OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
165	OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
166	OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
167	OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
168	OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
169	OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
170	/* Local pt_regs on stack in int frame form, plus 16 bytes for TM */
171	DEFINE(TM_FRAME_SIZE, STACK_INT_FRAME_SIZE + 16);
172#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
173
174	OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
175
176#ifdef CONFIG_PPC64
177	OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
178	OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
179	/* paca */
180	OFFSET(PACAPACAINDEX, paca_struct, paca_index);
181	OFFSET(PACAPROCSTART, paca_struct, cpu_start);
182	OFFSET(PACAKSAVE, paca_struct, kstack);
183	OFFSET(PACACURRENT, paca_struct, __current);
184	DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
185				 offsetof(struct task_struct, thread_info));
186	OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
187	OFFSET(PACAR1, paca_struct, saved_r1);
188#ifndef CONFIG_PPC_KERNEL_PCREL
189	OFFSET(PACATOC, paca_struct, kernel_toc);
190#endif
191	OFFSET(PACAKBASE, paca_struct, kernelbase);
192	OFFSET(PACAKMSR, paca_struct, kernel_msr);
193#ifdef CONFIG_PPC_BOOK3S_64
194	OFFSET(PACAHSRR_VALID, paca_struct, hsrr_valid);
195	OFFSET(PACASRR_VALID, paca_struct, srr_valid);
196#endif
197	OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
198	OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
199	OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
200
201#ifdef CONFIG_PPC_BOOK3E_64
202	OFFSET(PACAPGD, paca_struct, pgd);
203	OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
204	OFFSET(PACA_EXGEN, paca_struct, exgen);
205	OFFSET(PACA_EXTLB, paca_struct, extlb);
206	OFFSET(PACA_EXMC, paca_struct, exmc);
207	OFFSET(PACA_EXCRIT, paca_struct, excrit);
208	OFFSET(PACA_EXDBG, paca_struct, exdbg);
209	OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
210	OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
211	OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
212	OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
213
214	OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
215	OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
216	OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
217#endif /* CONFIG_PPC_BOOK3E_64 */
218
219#ifdef CONFIG_PPC_BOOK3S_64
220	OFFSET(PACA_EXGEN, paca_struct, exgen);
221	OFFSET(PACA_EXMC, paca_struct, exmc);
222	OFFSET(PACA_EXNMI, paca_struct, exnmi);
223#ifdef CONFIG_PPC_64S_HASH_MMU
224	OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
225	OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
226	OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
227	OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
228#endif
229	OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
230#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
231	OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
232#endif
233	OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
234#endif /* CONFIG_PPC_BOOK3S_64 */
235	OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
236#ifdef CONFIG_PPC_BOOK3S_64
237	OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
238	OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
239	OFFSET(PACA_IN_MCE, paca_struct, in_mce);
240	OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
241	OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
242	OFFSET(PACA_EXRFI, paca_struct, exrfi);
243	OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
244
245#endif
246	OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
247	OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
248	OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
249	OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1);
250#ifdef CONFIG_PPC_BOOK3E_64
251	OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
252#endif
253	OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
254#else /* CONFIG_PPC64 */
255#endif /* CONFIG_PPC64 */
256
257	/* RTAS */
258	OFFSET(RTASBASE, rtas_t, base);
259	OFFSET(RTASENTRY, rtas_t, entry);
260
261	/* Interrupt register frame */
262	DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
263	DEFINE(SWITCH_FRAME_SIZE, STACK_SWITCH_FRAME_SIZE);
264	STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
265	STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
266	STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
267	STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
268	STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
269	STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
270	STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
271	STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
272	STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
273	STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
274	STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
275	STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
276	STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
277	STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
278	/*
279	 * Note: these symbols include _ because they overlap with special
280	 * register names
281	 */
282	STACK_PT_REGS_OFFSET(_NIP, nip);
283	STACK_PT_REGS_OFFSET(_MSR, msr);
284	STACK_PT_REGS_OFFSET(_CTR, ctr);
285	STACK_PT_REGS_OFFSET(_LINK, link);
286	STACK_PT_REGS_OFFSET(_CCR, ccr);
287	STACK_PT_REGS_OFFSET(_XER, xer);
288	STACK_PT_REGS_OFFSET(_DAR, dar);
289	STACK_PT_REGS_OFFSET(_DEAR, dear);
290	STACK_PT_REGS_OFFSET(_DSISR, dsisr);
291	STACK_PT_REGS_OFFSET(_ESR, esr);
292	STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
293	STACK_PT_REGS_OFFSET(RESULT, result);
294	STACK_PT_REGS_OFFSET(_TRAP, trap);
295#ifdef CONFIG_PPC64
296	STACK_PT_REGS_OFFSET(SOFTE, softe);
297	STACK_PT_REGS_OFFSET(_PPR, ppr);
298#endif
299
300#ifdef CONFIG_PPC_PKEY
301	STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr);
302	STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
303#endif
304
305#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
306	STACK_PT_REGS_OFFSET(MAS0, mas0);
307	/* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
308	STACK_PT_REGS_OFFSET(MMUCR, mas0);
309	STACK_PT_REGS_OFFSET(MAS1, mas1);
310	STACK_PT_REGS_OFFSET(MAS2, mas2);
311	STACK_PT_REGS_OFFSET(MAS3, mas3);
312	STACK_PT_REGS_OFFSET(MAS6, mas6);
313	STACK_PT_REGS_OFFSET(MAS7, mas7);
314	STACK_PT_REGS_OFFSET(_SRR0, srr0);
315	STACK_PT_REGS_OFFSET(_SRR1, srr1);
316	STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
317	STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
318	STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
319	STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
320#endif
321
322	/* About the CPU features table */
323	OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
324	OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
325	OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
326
327	OFFSET(pbe_address, pbe, address);
328	OFFSET(pbe_orig_address, pbe, orig_address);
329	OFFSET(pbe_next, pbe, next);
330
331#ifndef CONFIG_PPC64
332	DEFINE(TASK_SIZE, TASK_SIZE);
333	DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
334#endif /* ! CONFIG_PPC64 */
335
336	/* datapage offsets for use by vdso */
337	OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data);
338	OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec);
339#ifdef CONFIG_PPC64
340	OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size);
341	OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size);
342	OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size);
343	OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size);
344	OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map);
345	OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map);
346#else
347	OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map);
348#endif
349
350#ifdef CONFIG_BUG
351	DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
352#endif
353
354#ifdef CONFIG_KVM
355	OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
356	OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
357	OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
358	OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
359	OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
360	OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
361#ifdef CONFIG_ALTIVEC
362	OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
363#endif
364	OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
365	OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
366	OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
367#ifdef CONFIG_PPC_BOOK3S
368	OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
369#endif
370	OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
371	OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
372#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
373	OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
374	OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
375	OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
376	OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
377	OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
378	OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
379	OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
380#endif
381#ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
382	OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
383	OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
384	OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
385	OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
386	OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
387	OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
388	OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
389	OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
390	OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
391	OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
392	OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
393#endif
394	OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
395	OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
396	OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
397	OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
398	OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
399	OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
400	OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
401	OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
402	OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
403	OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
404#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
405	OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
406#endif
407
408	OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
409	OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
410	OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
411	OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
412	OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
413	OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
414
415	OFFSET(VCPU_KVM, kvm_vcpu, kvm);
416	OFFSET(KVM_LPID, kvm, arch.lpid);
417
418	/* book3s */
419#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
420	OFFSET(KVM_SDR1, kvm, arch.sdr1);
421	OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
422	OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
423	OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
424	OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
425	OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
426	OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
427	OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
428	OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
429	OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
430	OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
431	OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
432	OFFSET(VCPU_CPU, kvm_vcpu, cpu);
433	OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
434#endif
435#ifdef CONFIG_PPC_BOOK3S
436	OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
437	OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
438	OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
439	OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
440	OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
441	OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
442	OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
443	OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
444	OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
445	OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
446	OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
447	OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
448	OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
449	OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
450	OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
451	OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
452	OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
453	OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
454	OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
455	OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
456	OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
457	OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
458	OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
459	OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
460	OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
461	OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
462	OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
463	OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
464	OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
465	OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
466	OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
467	OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
468	OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
469	OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
470	OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
471	OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
472	OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
473	OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
474	OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
475	OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
476	OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
477	OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
478	OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
479	OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
480	OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
481	OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
482	OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
483	OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
484	OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
485	OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
486	OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
487	OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
488	OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
489	OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
490	OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
491	OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
492	OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
493	OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
494	DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
495#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
496	OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
497	OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
498	OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
499	OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
500	OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
501	OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
502	OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
503	OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
504	OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
505	OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
506	OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
507	OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
508	OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
509	OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
510	OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
511	OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
512#endif
513
514#ifdef CONFIG_PPC_BOOK3S_64
515#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
516	OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
517# define SVCPU_FIELD(x, f)	DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
518#else
519# define SVCPU_FIELD(x, f)
520#endif
521# define HSTATE_FIELD(x, f)	DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
522#else	/* 32-bit */
523# define SVCPU_FIELD(x, f)	DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
524# define HSTATE_FIELD(x, f)	DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
525#endif
526
527	SVCPU_FIELD(SVCPU_CR, cr);
528	SVCPU_FIELD(SVCPU_XER, xer);
529	SVCPU_FIELD(SVCPU_CTR, ctr);
530	SVCPU_FIELD(SVCPU_LR, lr);
531	SVCPU_FIELD(SVCPU_PC, pc);
532	SVCPU_FIELD(SVCPU_R0, gpr[0]);
533	SVCPU_FIELD(SVCPU_R1, gpr[1]);
534	SVCPU_FIELD(SVCPU_R2, gpr[2]);
535	SVCPU_FIELD(SVCPU_R3, gpr[3]);
536	SVCPU_FIELD(SVCPU_R4, gpr[4]);
537	SVCPU_FIELD(SVCPU_R5, gpr[5]);
538	SVCPU_FIELD(SVCPU_R6, gpr[6]);
539	SVCPU_FIELD(SVCPU_R7, gpr[7]);
540	SVCPU_FIELD(SVCPU_R8, gpr[8]);
541	SVCPU_FIELD(SVCPU_R9, gpr[9]);
542	SVCPU_FIELD(SVCPU_R10, gpr[10]);
543	SVCPU_FIELD(SVCPU_R11, gpr[11]);
544	SVCPU_FIELD(SVCPU_R12, gpr[12]);
545	SVCPU_FIELD(SVCPU_R13, gpr[13]);
546	SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
547	SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
548	SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
549	SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
550#ifdef CONFIG_PPC_BOOK3S_32
551	SVCPU_FIELD(SVCPU_SR, sr);
552#endif
553#ifdef CONFIG_PPC64
554	SVCPU_FIELD(SVCPU_SLB, slb);
555	SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
556	SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
557#endif
558
559	HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
560	HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
561	HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
562	HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
563	HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
564	HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
565	HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
566	HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
567	HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
568	HSTATE_FIELD(HSTATE_NAPPING, napping);
569
570#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
571	HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
572	HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
573	HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
574	HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
575	HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
576	HSTATE_FIELD(HSTATE_PTID, ptid);
577	HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
578	HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
579	HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
580	HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
581	HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
582	HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
583	HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
584	HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
585	HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
586	HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
587	HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
588	HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
589	HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
590	HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
591	HSTATE_FIELD(HSTATE_PURR, host_purr);
592	HSTATE_FIELD(HSTATE_SPURR, host_spurr);
593	HSTATE_FIELD(HSTATE_DSCR, host_dscr);
594	HSTATE_FIELD(HSTATE_DABR, dabr);
595	HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
596	HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
597	DEFINE(IPI_PRIORITY, IPI_PRIORITY);
598	OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
599	OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
600	OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
601	OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
602	OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
603#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
604
605#ifdef CONFIG_PPC_BOOK3S_64
606	HSTATE_FIELD(HSTATE_CFAR, cfar);
607	HSTATE_FIELD(HSTATE_PPR, ppr);
608	HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
609#endif /* CONFIG_PPC_BOOK3S_64 */
610
611#else /* CONFIG_PPC_BOOK3S */
612	OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
613	OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
614	OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
615	OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
616	OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
617	OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
618	OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
619	OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
620	OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
621	OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
622#endif /* CONFIG_PPC_BOOK3S */
623#endif /* CONFIG_KVM */
624
625#ifdef CONFIG_KVM_GUEST
626	OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
627	OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
628	OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
629	OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
630	OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
631	OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
632	OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
633#endif
634
635#ifdef CONFIG_44x
636	DEFINE(PGD_T_LOG2, PGD_T_LOG2);
637	DEFINE(PTE_T_LOG2, PTE_T_LOG2);
638#endif
639#ifdef CONFIG_PPC_E500
640	DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
641	OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
642	OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
643	OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
644	OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
645	OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
646#endif
647
648#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
649	OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
650	OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
651	OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
652	OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
653#endif
654
655#ifdef CONFIG_KVM_BOOKE_HV
656	OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
657	OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
658#endif
659
660#ifdef CONFIG_KVM_EXIT_TIMING
661	OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
662	OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
663	OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
664	OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
665#endif
666
667	DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
668
669#ifdef CONFIG_PPC_8xx
670	DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
671#endif
672
673#ifdef CONFIG_XMON
674	DEFINE(BPT_SIZE, BPT_SIZE);
675#endif
676
677	return 0;
678}
679