1110386Sbenno/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2110386Sbenno/* 3110386Sbenno * Copyright (C) 2001 PPC64 Team, IBM Corp 4110386Sbenno * 5110386Sbenno * This struct defines the way the registers are stored on the 6110386Sbenno * kernel stack during a system call or other kernel entry. 7110386Sbenno * 8110386Sbenno * this should only contain volatile regs 9110386Sbenno * since we can keep non-volatile in the thread_struct 10110386Sbenno * should set this up when only volatiles are saved 11110386Sbenno * by intr code. 12110386Sbenno * 13110386Sbenno * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 14110386Sbenno * that the overall structure is a multiple of 16 bytes in length. 15110386Sbenno * 16110386Sbenno * Note that the offsets of the fields in this struct correspond with 17110386Sbenno * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 18110386Sbenno * 19110386Sbenno * This program is free software; you can redistribute it and/or 20110386Sbenno * modify it under the terms of the GNU General Public License 21110386Sbenno * as published by the Free Software Foundation; either version 22110386Sbenno * 2 of the License, or (at your option) any later version. 23110386Sbenno */ 24110386Sbenno#ifndef _UAPI_ASM_POWERPC_PTRACE_H 25110386Sbenno#define _UAPI_ASM_POWERPC_PTRACE_H 26110386Sbenno 27110386Sbenno 28110386Sbenno#include <linux/types.h> 29110386Sbenno 30110386Sbenno#ifndef __ASSEMBLY__ 31110386Sbenno 32110386Sbenno#ifdef __KERNEL__ 33139825Simpstruct user_pt_regs 34110386Sbenno#else 35110386Sbennostruct pt_regs 36110386Sbenno#endif 37110386Sbenno{ 38110386Sbenno unsigned long gpr[32]; 39110386Sbenno unsigned long nip; 40110386Sbenno unsigned long msr; 41110386Sbenno unsigned long orig_gpr3; /* Used for restarting system calls */ 42110386Sbenno unsigned long ctr; 43110386Sbenno unsigned long link; 44110386Sbenno unsigned long xer; 45110386Sbenno unsigned long ccr; 46110386Sbenno#ifdef __powerpc64__ 47110386Sbenno unsigned long softe; /* Soft enabled/disabled */ 48110386Sbenno#else 49110386Sbenno unsigned long mq; /* 601 only (not used at present) */ 50110386Sbenno /* Used on APUS to hold IPL value. */ 51110386Sbenno#endif 52110386Sbenno unsigned long trap; /* Reason for being here */ 53110386Sbenno /* N.B. for critical exceptions on 4xx, the dar and dsisr 54110386Sbenno fields are overloaded to hold srr0 and srr1. */ 55110386Sbenno unsigned long dar; /* Fault registers */ 56110386Sbenno unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 57110386Sbenno unsigned long result; /* Result of a system call */ 58110386Sbenno}; 59110386Sbenno 60110386Sbenno#endif /* __ASSEMBLY__ */ 61110386Sbenno 62110386Sbenno 63110386Sbenno/* 64110386Sbenno * Offsets used by 'ptrace' system call interface. 65193156Snwhitehorn * These can't be changed without breaking binary compatibility 66110386Sbenno * with MkLinux, etc. 67166011Smarcel */ 68110386Sbenno#define PT_R0 0 69110386Sbenno#define PT_R1 1 70110386Sbenno#define PT_R2 2 71110386Sbenno#define PT_R3 3 72110386Sbenno#define PT_R4 4 73110386Sbenno#define PT_R5 5 74176919Smarcel#define PT_R6 6 75176919Smarcel#define PT_R7 7 76110386Sbenno#define PT_R8 8 77110386Sbenno#define PT_R9 9 78110386Sbenno#define PT_R10 10 79110386Sbenno#define PT_R11 11 80110386Sbenno#define PT_R12 12 81110386Sbenno#define PT_R13 13 82110386Sbenno#define PT_R14 14 83110386Sbenno#define PT_R15 15 84110386Sbenno#define PT_R16 16 85110386Sbenno#define PT_R17 17 86110386Sbenno#define PT_R18 18 87110386Sbenno#define PT_R19 19 88110386Sbenno#define PT_R20 20 89110386Sbenno#define PT_R21 21 90110386Sbenno#define PT_R22 22 91110386Sbenno#define PT_R23 23 92110386Sbenno#define PT_R24 24 93110386Sbenno#define PT_R25 25 94110386Sbenno#define PT_R26 26 95190681Snwhitehorn#define PT_R27 27 96190681Snwhitehorn#define PT_R28 28 97190681Snwhitehorn#define PT_R29 29 98190681Snwhitehorn#define PT_R30 30 99110386Sbenno#define PT_R31 31 100110386Sbenno 101110386Sbenno#define PT_NIP 32 102110386Sbenno#define PT_MSR 33 103125615Sgrehan#define PT_ORIG_R3 34 104141229Sgrehan#define PT_CTR 35 105141229Sgrehan#define PT_LNK 36 106110386Sbenno#define PT_XER 37 107176534Sraj#define PT_CCR 38 108176534Sraj#ifndef __powerpc64__ 109110386Sbenno#define PT_MQ 39 110110386Sbenno#else 111110386Sbenno#define PT_SOFTE 39 112166011Smarcel#endif 113166011Smarcel#define PT_TRAP 40 114166011Smarcel#define PT_DAR 41 115183029Smarcel#define PT_DSISR 42 116183029Smarcel#define PT_RESULT 43 117110386Sbenno#define PT_DSCR 44 118110386Sbenno#define PT_REGS_COUNT 44 119183029Smarcel 120110386Sbenno#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 121110386Sbenno 122110386Sbenno#ifndef __powerpc64__ 123110386Sbenno 124110386Sbenno#define PT_FPR31 (PT_FPR0 + 2*31) 125110386Sbenno#define PT_FPSCR (PT_FPR0 + 2*32 + 1) 126110386Sbenno 127110386Sbenno#else /* __powerpc64__ */ 128110386Sbenno 129110386Sbenno#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 130110386Sbenno 131110386Sbenno 132110386Sbenno#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 133110386Sbenno#define PT_VSCR (PT_VR0 + 32*2 + 1) 134176534Sraj#define PT_VRSAVE (PT_VR0 + 33*2) 135176534Sraj 136176534Sraj 137176534Sraj/* 138176534Sraj * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 139176534Sraj */ 140176534Sraj#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 141176534Sraj#define PT_VSR31 (PT_VSR0 + 2*31) 142176534Sraj#endif /* __powerpc64__ */ 143176534Sraj 144176534Sraj/* 145176534Sraj * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go. 146110386Sbenno * The transfer totals 34 quadword. Quadwords 0-31 contain the 147110386Sbenno * corresponding vector registers. Quadword 32 contains the vscr as the 148166812Smarcel * last word (offset 12) within that quadword. Quadword 33 contains the 149110386Sbenno * vrsave as the first word (offset 0) within the quadword. 150110386Sbenno * 151110386Sbenno * This definition of the VMX state is compatible with the current PPC32 152110386Sbenno * ptrace interface. This allows signal handling and ptrace to use the same 153110386Sbenno * structures. This also simplifies the implementation of a bi-arch 154110386Sbenno * (combined (32- and 64-bit) gdb. 155110386Sbenno */ 156110386Sbenno#define PTRACE_GETVRREGS 0x12 157110386Sbenno#define PTRACE_SETVRREGS 0x13 158110386Sbenno 159166011Smarcel/* Get/set all the upper 32-bits of the SPE registers, accumulator, and 160110386Sbenno * spefscr, in one go */ 161110386Sbenno#define PTRACE_GETEVRREGS 0x14 162110386Sbenno#define PTRACE_SETEVRREGS 0x15 163110386Sbenno 164176534Sraj/* Get the first 32 128bit VSX registers */ 165176534Sraj#define PTRACE_GETVSRREGS 0x1b 166176534Sraj#define PTRACE_SETVSRREGS 0x1c 167176534Sraj 168176534Sraj/* Syscall emulation defines */ 169176534Sraj#define PTRACE_SYSEMU 0x1d 170176534Sraj#define PTRACE_SYSEMU_SINGLESTEP 0x1e 171176534Sraj 172176534Sraj/* 173110386Sbenno * Get or set a debug register. The first 16 are DABR registers and the 174110386Sbenno * second 16 are IABR registers. 175110386Sbenno */ 176110386Sbenno#define PTRACE_GET_DEBUGREG 0x19 177110386Sbenno#define PTRACE_SET_DEBUGREG 0x1a 178110386Sbenno 179110386Sbenno/* (new) PTRACE requests using the same numbers as x86 and the same 180110386Sbenno * argument ordering. Additionally, they support more registers too 181176534Sraj */ 182176534Sraj#define PTRACE_GETREGS 0xc 183176534Sraj#define PTRACE_SETREGS 0xd 184176534Sraj#define PTRACE_GETFPREGS 0xe 185176534Sraj#define PTRACE_SETFPREGS 0xf 186176534Sraj#define PTRACE_GETREGS64 0x16 187176534Sraj#define PTRACE_SETREGS64 0x17 188176534Sraj 189176534Sraj/* Calls to trace a 64bit program from a 32bit program */ 190176534Sraj#define PPC_PTRACE_PEEKTEXT_3264 0x95 191176534Sraj#define PPC_PTRACE_PEEKDATA_3264 0x94 192176534Sraj#define PPC_PTRACE_POKETEXT_3264 0x93 193176534Sraj#define PPC_PTRACE_POKEDATA_3264 0x92 194176919Smarcel#define PPC_PTRACE_PEEKUSR_3264 0x91 195176534Sraj#define PPC_PTRACE_POKEUSR_3264 0x90 196110386Sbenno 197176534Sraj#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 198176534Sraj 199176534Sraj#define PPC_PTRACE_GETHWDBGINFO 0x89 200176534Sraj#define PPC_PTRACE_SETHWDEBUG 0x88 201176534Sraj#define PPC_PTRACE_DELHWDEBUG 0x87 202176534Sraj 203176534Sraj#ifndef __ASSEMBLY__ 204176534Sraj 205176534Srajstruct ppc_debug_info { 206176534Sraj __u32 version; /* Only version 1 exists to date */ 207176534Sraj __u32 num_instruction_bps; 208176534Sraj __u32 num_data_bps; 209176534Sraj __u32 num_condition_regs; 210176534Sraj __u32 data_bp_alignment; 211176534Sraj __u32 sizeof_condition; /* size of the DVC register */ 212176919Smarcel __u64 features; 213176534Sraj}; 214110386Sbenno 215176534Sraj#endif /* __ASSEMBLY__ */ 216176534Sraj 217110386Sbenno/* 218110386Sbenno * features will have bits indication whether there is support for: 219110386Sbenno */ 220176534Sraj#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 221176534Sraj#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 222176534Sraj#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 223176534Sraj#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 224176534Sraj#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010 225110386Sbenno#define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x0000000000000020 226176534Sraj 227176534Sraj#ifndef __ASSEMBLY__ 228176534Sraj 229176534Srajstruct ppc_hw_breakpoint { 230176534Sraj __u32 version; /* currently, version must be 1 */ 231176534Sraj __u32 trigger_type; /* only some combinations allowed */ 232176534Sraj __u32 addr_mode; /* address match mode */ 233176534Sraj __u32 condition_mode; /* break/watchpoint condition flags */ 234176534Sraj __u64 addr; /* break/watchpoint address */ 235176534Sraj __u64 addr2; /* range end or mask */ 236110386Sbenno __u64 condition_value; /* contents of the DVC register */ 237110386Sbenno}; 238110386Sbenno 239110386Sbenno#endif /* __ASSEMBLY__ */ 240110386Sbenno 241176534Sraj/* 242176534Sraj * Trigger Type 243176534Sraj */ 244176534Sraj#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 245176534Sraj#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 246176534Sraj#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 247176534Sraj#define PPC_BREAKPOINT_TRIGGER_RW \ 248176534Sraj (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 249176534Sraj 250176534Sraj/* 251176534Sraj * Address Mode 252176534Sraj */ 253176534Sraj#define PPC_BREAKPOINT_MODE_EXACT 0x00000000 254176534Sraj#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 255110386Sbenno#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 256110386Sbenno#define PPC_BREAKPOINT_MODE_MASK 0x00000003 257110386Sbenno 258176534Sraj/* 259176534Sraj * Condition Mode 260176534Sraj */ 261183437Snwhitehorn#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 262183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 263183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_AND 0x00000001 264183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 265183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_OR 0x00000002 266183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 267183262Snwhitehorn#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 268183437Snwhitehorn#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 269183437Snwhitehorn#define PPC_BREAKPOINT_CONDITION_BE(n) \ 270183437Snwhitehorn (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 271183437Snwhitehorn 272176534Sraj#endif /* _UAPI_ASM_POWERPC_PTRACE_H */ 273176534Sraj