1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2/* 3 * Copyright (C) 2001 PPC64 Team, IBM Corp 4 * 5 * This struct defines the way the registers are stored on the 6 * kernel stack during a system call or other kernel entry. 7 * 8 * this should only contain volatile regs 9 * since we can keep non-volatile in the thread_struct 10 * should set this up when only volatiles are saved 11 * by intr code. 12 * 13 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 14 * that the overall structure is a multiple of 16 bytes in length. 15 * 16 * Note that the offsets of the fields in this struct correspond with 17 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24#ifndef _UAPI_ASM_POWERPC_PTRACE_H 25#define _UAPI_ASM_POWERPC_PTRACE_H 26 27 28#include <linux/types.h> 29 30#ifndef __ASSEMBLY__ 31 32#ifdef __KERNEL__ 33struct user_pt_regs 34#else 35struct pt_regs 36#endif 37{ 38 unsigned long gpr[32]; 39 unsigned long nip; 40 unsigned long msr; 41 unsigned long orig_gpr3; /* Used for restarting system calls */ 42 unsigned long ctr; 43 unsigned long link; 44 unsigned long xer; 45 unsigned long ccr; 46#ifdef __powerpc64__ 47 unsigned long softe; /* Soft enabled/disabled */ 48#else 49 unsigned long mq; /* 601 only (not used at present) */ 50 /* Used on APUS to hold IPL value. */ 51#endif 52 unsigned long trap; /* Reason for being here */ 53 /* N.B. for critical exceptions on 4xx, the dar and dsisr 54 fields are overloaded to hold srr0 and srr1. */ 55 unsigned long dar; /* Fault registers */ 56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 57 unsigned long result; /* Result of a system call */ 58}; 59 60#endif /* __ASSEMBLY__ */ 61 62 63/* 64 * Offsets used by 'ptrace' system call interface. 65 * These can't be changed without breaking binary compatibility 66 * with MkLinux, etc. 67 */ 68#define PT_R0 0 69#define PT_R1 1 70#define PT_R2 2 71#define PT_R3 3 72#define PT_R4 4 73#define PT_R5 5 74#define PT_R6 6 75#define PT_R7 7 76#define PT_R8 8 77#define PT_R9 9 78#define PT_R10 10 79#define PT_R11 11 80#define PT_R12 12 81#define PT_R13 13 82#define PT_R14 14 83#define PT_R15 15 84#define PT_R16 16 85#define PT_R17 17 86#define PT_R18 18 87#define PT_R19 19 88#define PT_R20 20 89#define PT_R21 21 90#define PT_R22 22 91#define PT_R23 23 92#define PT_R24 24 93#define PT_R25 25 94#define PT_R26 26 95#define PT_R27 27 96#define PT_R28 28 97#define PT_R29 29 98#define PT_R30 30 99#define PT_R31 31 100 101#define PT_NIP 32 102#define PT_MSR 33 103#define PT_ORIG_R3 34 104#define PT_CTR 35 105#define PT_LNK 36 106#define PT_XER 37 107#define PT_CCR 38 108#ifndef __powerpc64__ 109#define PT_MQ 39 110#else 111#define PT_SOFTE 39 112#endif 113#define PT_TRAP 40 114#define PT_DAR 41 115#define PT_DSISR 42 116#define PT_RESULT 43 117#define PT_DSCR 44 118#define PT_REGS_COUNT 44 119 120#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 121 122#ifndef __powerpc64__ 123 124#define PT_FPR31 (PT_FPR0 + 2*31) 125#define PT_FPSCR (PT_FPR0 + 2*32 + 1) 126 127#else /* __powerpc64__ */ 128 129#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 130 131 132#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 133#define PT_VSCR (PT_VR0 + 32*2 + 1) 134#define PT_VRSAVE (PT_VR0 + 33*2) 135 136 137/* 138 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 139 */ 140#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 141#define PT_VSR31 (PT_VSR0 + 2*31) 142#endif /* __powerpc64__ */ 143 144/* 145 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go. 146 * The transfer totals 34 quadword. Quadwords 0-31 contain the 147 * corresponding vector registers. Quadword 32 contains the vscr as the 148 * last word (offset 12) within that quadword. Quadword 33 contains the 149 * vrsave as the first word (offset 0) within the quadword. 150 * 151 * This definition of the VMX state is compatible with the current PPC32 152 * ptrace interface. This allows signal handling and ptrace to use the same 153 * structures. This also simplifies the implementation of a bi-arch 154 * (combined (32- and 64-bit) gdb. 155 */ 156#define PTRACE_GETVRREGS 0x12 157#define PTRACE_SETVRREGS 0x13 158 159/* Get/set all the upper 32-bits of the SPE registers, accumulator, and 160 * spefscr, in one go */ 161#define PTRACE_GETEVRREGS 0x14 162#define PTRACE_SETEVRREGS 0x15 163 164/* Get the first 32 128bit VSX registers */ 165#define PTRACE_GETVSRREGS 0x1b 166#define PTRACE_SETVSRREGS 0x1c 167 168/* Syscall emulation defines */ 169#define PTRACE_SYSEMU 0x1d 170#define PTRACE_SYSEMU_SINGLESTEP 0x1e 171 172/* 173 * Get or set a debug register. The first 16 are DABR registers and the 174 * second 16 are IABR registers. 175 */ 176#define PTRACE_GET_DEBUGREG 0x19 177#define PTRACE_SET_DEBUGREG 0x1a 178 179/* (new) PTRACE requests using the same numbers as x86 and the same 180 * argument ordering. Additionally, they support more registers too 181 */ 182#define PTRACE_GETREGS 0xc 183#define PTRACE_SETREGS 0xd 184#define PTRACE_GETFPREGS 0xe 185#define PTRACE_SETFPREGS 0xf 186#define PTRACE_GETREGS64 0x16 187#define PTRACE_SETREGS64 0x17 188 189/* Calls to trace a 64bit program from a 32bit program */ 190#define PPC_PTRACE_PEEKTEXT_3264 0x95 191#define PPC_PTRACE_PEEKDATA_3264 0x94 192#define PPC_PTRACE_POKETEXT_3264 0x93 193#define PPC_PTRACE_POKEDATA_3264 0x92 194#define PPC_PTRACE_PEEKUSR_3264 0x91 195#define PPC_PTRACE_POKEUSR_3264 0x90 196 197#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 198 199#define PPC_PTRACE_GETHWDBGINFO 0x89 200#define PPC_PTRACE_SETHWDEBUG 0x88 201#define PPC_PTRACE_DELHWDEBUG 0x87 202 203#ifndef __ASSEMBLY__ 204 205struct ppc_debug_info { 206 __u32 version; /* Only version 1 exists to date */ 207 __u32 num_instruction_bps; 208 __u32 num_data_bps; 209 __u32 num_condition_regs; 210 __u32 data_bp_alignment; 211 __u32 sizeof_condition; /* size of the DVC register */ 212 __u64 features; 213}; 214 215#endif /* __ASSEMBLY__ */ 216 217/* 218 * features will have bits indication whether there is support for: 219 */ 220#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 221#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 222#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 223#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 224#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010 225#define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x0000000000000020 226 227#ifndef __ASSEMBLY__ 228 229struct ppc_hw_breakpoint { 230 __u32 version; /* currently, version must be 1 */ 231 __u32 trigger_type; /* only some combinations allowed */ 232 __u32 addr_mode; /* address match mode */ 233 __u32 condition_mode; /* break/watchpoint condition flags */ 234 __u64 addr; /* break/watchpoint address */ 235 __u64 addr2; /* range end or mask */ 236 __u64 condition_value; /* contents of the DVC register */ 237}; 238 239#endif /* __ASSEMBLY__ */ 240 241/* 242 * Trigger Type 243 */ 244#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 245#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 246#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 247#define PPC_BREAKPOINT_TRIGGER_RW \ 248 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 249 250/* 251 * Address Mode 252 */ 253#define PPC_BREAKPOINT_MODE_EXACT 0x00000000 254#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 255#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 256#define PPC_BREAKPOINT_MODE_MASK 0x00000003 257 258/* 259 * Condition Mode 260 */ 261#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 262#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 263#define PPC_BREAKPOINT_CONDITION_AND 0x00000001 264#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 265#define PPC_BREAKPOINT_CONDITION_OR 0x00000002 266#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 267#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 268#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 269#define PPC_BREAKPOINT_CONDITION_BE(n) \ 270 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 271 272#endif /* _UAPI_ASM_POWERPC_PTRACE_H */ 273