1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_NOHASH_PTE_E500_H 3#define _ASM_POWERPC_NOHASH_PTE_E500_H 4#ifdef __KERNEL__ 5 6/* PTE bit definitions for processors compliant to the Book3E 7 * architecture 2.06 or later. The position of the PTE bits 8 * matches the HW definition of the optional Embedded Page Table 9 * category. 10 */ 11 12/* Architected bits */ 13#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */ 14#define _PAGE_SW1 0x000002 15#define _PAGE_BAP_SR 0x000004 16#define _PAGE_BAP_UR 0x000008 17#define _PAGE_BAP_SW 0x000010 18#define _PAGE_BAP_UW 0x000020 19#define _PAGE_BAP_SX 0x000040 20#define _PAGE_BAP_UX 0x000080 21#define _PAGE_PSIZE_MSK 0x000f00 22#define _PAGE_PSIZE_4K 0x000200 23#define _PAGE_PSIZE_8K 0x000300 24#define _PAGE_PSIZE_16K 0x000400 25#define _PAGE_PSIZE_32K 0x000500 26#define _PAGE_PSIZE_64K 0x000600 27#define _PAGE_PSIZE_128K 0x000700 28#define _PAGE_PSIZE_256K 0x000800 29#define _PAGE_PSIZE_512K 0x000900 30#define _PAGE_PSIZE_1M 0x000a00 31#define _PAGE_PSIZE_2M 0x000b00 32#define _PAGE_PSIZE_4M 0x000c00 33#define _PAGE_PSIZE_8M 0x000d00 34#define _PAGE_PSIZE_16M 0x000e00 35#define _PAGE_PSIZE_32M 0x000f00 36#define _PAGE_DIRTY 0x001000 /* C: page changed */ 37#define _PAGE_SW0 0x002000 38#define _PAGE_U3 0x004000 39#define _PAGE_U2 0x008000 40#define _PAGE_U1 0x010000 41#define _PAGE_U0 0x020000 42#define _PAGE_ACCESSED 0x040000 43#define _PAGE_ENDIAN 0x080000 44#define _PAGE_GUARDED 0x100000 45#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */ 46#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */ 47#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */ 48 49/* "Higher level" linux bit combinations */ 50#define _PAGE_EXEC (_PAGE_BAP_SX | _PAGE_BAP_UX) /* .. and was cache cleaned */ 51#define _PAGE_READ (_PAGE_BAP_SR | _PAGE_BAP_UR) /* User read permission */ 52#define _PAGE_WRITE (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */ 53 54#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY) 55#define _PAGE_KERNEL_RO (_PAGE_BAP_SR) 56#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX) 57#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX) 58 59#define _PAGE_NA 0 60#define _PAGE_NAX _PAGE_BAP_UX 61#define _PAGE_RO _PAGE_READ 62#define _PAGE_ROX (_PAGE_READ | _PAGE_BAP_UX) 63#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 64#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_BAP_UX) 65 66#define _PAGE_SPECIAL _PAGE_SW0 67 68/* Base page size */ 69#define _PAGE_PSIZE _PAGE_PSIZE_4K 70#define PTE_RPN_SHIFT (24) 71 72#define PTE_WIMGE_SHIFT (19) 73#define PTE_BAP_SHIFT (2) 74 75/* On 32-bit, we never clear the top part of the PTE */ 76#ifdef CONFIG_PPC32 77#define _PTE_NONE_MASK 0xffffffff00000000ULL 78#define _PMD_PRESENT 0 79#define _PMD_PRESENT_MASK (PAGE_MASK) 80#define _PMD_BAD (~PAGE_MASK) 81#define _PMD_USER 0 82#else 83#define _PTE_NONE_MASK 0 84#endif 85 86/* 87 * We define 2 sets of base prot bits, one for basic pages (ie, 88 * cacheable kernel and user pages) and one for non cacheable 89 * pages. We always set _PAGE_COHERENT when SMP is enabled or 90 * the processor might need it for DMA coherency. 91 */ 92#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 93#if defined(CONFIG_SMP) 94#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 95#else 96#define _PAGE_BASE (_PAGE_BASE_NC) 97#endif 98 99#include <asm/pgtable-masks.h> 100 101#ifndef __ASSEMBLY__ 102static inline pte_t pte_mkexec(pte_t pte) 103{ 104 return __pte((pte_val(pte) & ~_PAGE_BAP_SX) | _PAGE_BAP_UX); 105} 106#define pte_mkexec pte_mkexec 107 108#endif /* __ASSEMBLY__ */ 109 110#endif /* __KERNEL__ */ 111#endif /* _ASM_POWERPC_NOHASH_PTE_E500_H */ 112