1// SPDX-License-Identifier: GPL-2.0 2#include <linux/err.h> 3#include <linux/slab.h> 4#include <linux/mm_types.h> 5#include <linux/sched/task.h> 6 7#include <asm/branch.h> 8#include <asm/cacheflush.h> 9#include <asm/fpu_emulator.h> 10#include <asm/inst.h> 11#include <asm/mipsregs.h> 12#include <linux/uaccess.h> 13 14/** 15 * struct emuframe - The 'emulation' frame structure 16 * @emul: The instruction to 'emulate'. 17 * @badinst: A break instruction to cause a return to the kernel. 18 * 19 * This structure defines the frames placed within the delay slot emulation 20 * page in response to a call to mips_dsemul(). Each thread may be allocated 21 * only one frame at any given time. The kernel stores within it the 22 * instruction to be 'emulated' followed by a break instruction, then 23 * executes the frame in user mode. The break causes a trap to the kernel 24 * which leads to do_dsemulret() being called unless the instruction in 25 * @emul causes a trap itself, is a branch, or a signal is delivered to 26 * the thread. In these cases the allocated frame will either be reused by 27 * a subsequent delay slot 'emulation', or be freed during signal delivery or 28 * upon thread exit. 29 * 30 * This approach is used because: 31 * 32 * - Actually emulating all instructions isn't feasible. We would need to 33 * be able to handle instructions from all revisions of the MIPS ISA, 34 * all ASEs & all vendor instruction set extensions. This would be a 35 * whole lot of work & continual maintenance burden as new instructions 36 * are introduced, and in the case of some vendor extensions may not 37 * even be possible. Thus we need to take the approach of actually 38 * executing the instruction. 39 * 40 * - We must execute the instruction within user context. If we were to 41 * execute the instruction in kernel mode then it would have access to 42 * kernel resources without very careful checks, leaving us with a 43 * high potential for security or stability issues to arise. 44 * 45 * - We used to place the frame on the users stack, but this requires 46 * that the stack be executable. This is bad for security so the 47 * per-process page is now used instead. 48 * 49 * - The instruction in @emul may be something entirely invalid for a 50 * delay slot. The user may (intentionally or otherwise) place a branch 51 * in a delay slot, or a kernel mode instruction, or something else 52 * which generates an exception. Thus we can't rely upon the break in 53 * @badinst always being hit. For this reason we track the index of the 54 * frame allocated to each thread, allowing us to clean it up at later 55 * points such as signal delivery or thread exit. 56 * 57 * - The user may generate a fake struct emuframe if they wish, invoking 58 * the BRK_MEMU break instruction themselves. We must therefore not 59 * trust that BRK_MEMU means there's actually a valid frame allocated 60 * to the thread, and must not allow the user to do anything they 61 * couldn't already. 62 */ 63struct emuframe { 64 mips_instruction emul; 65 mips_instruction badinst; 66}; 67 68static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe); 69 70static inline __user struct emuframe *dsemul_page(void) 71{ 72 return (__user struct emuframe *)STACK_TOP; 73} 74 75static int alloc_emuframe(void) 76{ 77 mm_context_t *mm_ctx = ¤t->mm->context; 78 int idx; 79 80retry: 81 spin_lock(&mm_ctx->bd_emupage_lock); 82 83 /* Ensure we have an allocation bitmap */ 84 if (!mm_ctx->bd_emupage_allocmap) { 85 mm_ctx->bd_emupage_allocmap = bitmap_zalloc(emupage_frame_count, 86 GFP_ATOMIC); 87 if (!mm_ctx->bd_emupage_allocmap) { 88 idx = BD_EMUFRAME_NONE; 89 goto out_unlock; 90 } 91 } 92 93 /* Attempt to allocate a single bit/frame */ 94 idx = bitmap_find_free_region(mm_ctx->bd_emupage_allocmap, 95 emupage_frame_count, 0); 96 if (idx < 0) { 97 /* 98 * Failed to allocate a frame. We'll wait until one becomes 99 * available. We unlock the page so that other threads actually 100 * get the opportunity to free their frames, which means 101 * technically the result of bitmap_full may be incorrect. 102 * However the worst case is that we repeat all this and end up 103 * back here again. 104 */ 105 spin_unlock(&mm_ctx->bd_emupage_lock); 106 if (!wait_event_killable(mm_ctx->bd_emupage_queue, 107 !bitmap_full(mm_ctx->bd_emupage_allocmap, 108 emupage_frame_count))) 109 goto retry; 110 111 /* Received a fatal signal - just give in */ 112 return BD_EMUFRAME_NONE; 113 } 114 115 /* Success! */ 116 pr_debug("allocate emuframe %d to %d\n", idx, current->pid); 117out_unlock: 118 spin_unlock(&mm_ctx->bd_emupage_lock); 119 return idx; 120} 121 122static void free_emuframe(int idx, struct mm_struct *mm) 123{ 124 mm_context_t *mm_ctx = &mm->context; 125 126 spin_lock(&mm_ctx->bd_emupage_lock); 127 128 pr_debug("free emuframe %d from %d\n", idx, current->pid); 129 bitmap_clear(mm_ctx->bd_emupage_allocmap, idx, 1); 130 131 /* If some thread is waiting for a frame, now's its chance */ 132 wake_up(&mm_ctx->bd_emupage_queue); 133 134 spin_unlock(&mm_ctx->bd_emupage_lock); 135} 136 137static bool within_emuframe(struct pt_regs *regs) 138{ 139 unsigned long base = (unsigned long)dsemul_page(); 140 141 if (regs->cp0_epc < base) 142 return false; 143 if (regs->cp0_epc >= (base + PAGE_SIZE)) 144 return false; 145 146 return true; 147} 148 149bool dsemul_thread_cleanup(struct task_struct *tsk) 150{ 151 int fr_idx; 152 153 /* Clear any allocated frame, retrieving its index */ 154 fr_idx = atomic_xchg(&tsk->thread.bd_emu_frame, BD_EMUFRAME_NONE); 155 156 /* If no frame was allocated, we're done */ 157 if (fr_idx == BD_EMUFRAME_NONE) 158 return false; 159 160 task_lock(tsk); 161 162 /* Free the frame that this thread had allocated */ 163 if (tsk->mm) 164 free_emuframe(fr_idx, tsk->mm); 165 166 task_unlock(tsk); 167 return true; 168} 169 170bool dsemul_thread_rollback(struct pt_regs *regs) 171{ 172 struct emuframe __user *fr; 173 int fr_idx; 174 175 /* Do nothing if we're not executing from a frame */ 176 if (!within_emuframe(regs)) 177 return false; 178 179 /* Find the frame being executed */ 180 fr_idx = atomic_read(¤t->thread.bd_emu_frame); 181 if (fr_idx == BD_EMUFRAME_NONE) 182 return false; 183 fr = &dsemul_page()[fr_idx]; 184 185 /* 186 * If the PC is at the emul instruction, roll back to the branch. If 187 * PC is at the badinst (break) instruction, we've already emulated the 188 * instruction so progress to the continue PC. If it's anything else 189 * then something is amiss & the user has branched into some other area 190 * of the emupage - we'll free the allocated frame anyway. 191 */ 192 if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->emul) 193 regs->cp0_epc = current->thread.bd_emu_branch_pc; 194 else if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->badinst) 195 regs->cp0_epc = current->thread.bd_emu_cont_pc; 196 197 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); 198 free_emuframe(fr_idx, current->mm); 199 return true; 200} 201 202void dsemul_mm_cleanup(struct mm_struct *mm) 203{ 204 mm_context_t *mm_ctx = &mm->context; 205 206 bitmap_free(mm_ctx->bd_emupage_allocmap); 207} 208 209int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 210 unsigned long branch_pc, unsigned long cont_pc) 211{ 212 int isa16 = get_isa16_mode(regs->cp0_epc); 213 mips_instruction break_math; 214 unsigned long fr_uaddr; 215 struct emuframe fr; 216 int fr_idx, ret; 217 218 /* NOP is easy */ 219 if (ir == 0) 220 return -1; 221 222 /* microMIPS instructions */ 223 if (isa16) { 224 union mips_instruction insn = { .word = ir }; 225 226 /* NOP16 aka MOVE16 $0, $0 */ 227 if ((ir >> 16) == MM_NOP16) 228 return -1; 229 230 /* ADDIUPC */ 231 if (insn.mm_a_format.opcode == mm_addiupc_op) { 232 unsigned int rs; 233 s32 v; 234 235 rs = (((insn.mm_a_format.rs + 0xe) & 0xf) + 2); 236 v = regs->cp0_epc & ~3; 237 v += insn.mm_a_format.simmediate << 2; 238 regs->regs[rs] = (long)v; 239 return -1; 240 } 241 } 242 243 pr_debug("dsemul 0x%08lx cont at 0x%08lx\n", regs->cp0_epc, cont_pc); 244 245 /* Allocate a frame if we don't already have one */ 246 fr_idx = atomic_read(¤t->thread.bd_emu_frame); 247 if (fr_idx == BD_EMUFRAME_NONE) 248 fr_idx = alloc_emuframe(); 249 if (fr_idx == BD_EMUFRAME_NONE) 250 return SIGBUS; 251 252 /* Retrieve the appropriately encoded break instruction */ 253 break_math = BREAK_MATH(isa16); 254 255 /* Write the instructions to the frame */ 256 if (isa16) { 257 union mips_instruction _emul = { 258 .halfword = { ir >> 16, ir } 259 }; 260 union mips_instruction _badinst = { 261 .halfword = { break_math >> 16, break_math } 262 }; 263 264 fr.emul = _emul.word; 265 fr.badinst = _badinst.word; 266 } else { 267 fr.emul = ir; 268 fr.badinst = break_math; 269 } 270 271 /* Write the frame to user memory */ 272 fr_uaddr = (unsigned long)&dsemul_page()[fr_idx]; 273 ret = access_process_vm(current, fr_uaddr, &fr, sizeof(fr), 274 FOLL_FORCE | FOLL_WRITE); 275 if (unlikely(ret != sizeof(fr))) { 276 MIPS_FPU_EMU_INC_STATS(errors); 277 free_emuframe(fr_idx, current->mm); 278 return SIGBUS; 279 } 280 281 /* Record the PC of the branch, PC to continue from & frame index */ 282 current->thread.bd_emu_branch_pc = branch_pc; 283 current->thread.bd_emu_cont_pc = cont_pc; 284 atomic_set(¤t->thread.bd_emu_frame, fr_idx); 285 286 /* Change user register context to execute the frame */ 287 regs->cp0_epc = fr_uaddr | isa16; 288 289 return 0; 290} 291 292bool do_dsemulret(struct pt_regs *xcp) 293{ 294 /* Cleanup the allocated frame, returning if there wasn't one */ 295 if (!dsemul_thread_cleanup(current)) { 296 MIPS_FPU_EMU_INC_STATS(errors); 297 return false; 298 } 299 300 /* Set EPC to return to post-branch instruction */ 301 xcp->cp0_epc = current->thread.bd_emu_cont_pc; 302 pr_debug("dsemulret to 0x%08lx\n", xcp->cp0_epc); 303 MIPS_FPU_EMU_INC_STATS(ds_emul); 304 return true; 305} 306