1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * loongson-specific suspend support
4 *
5 *  Copyright (C) 2009 Lemote Inc.
6 *  Author: Wu Zhangjin <wuzhangjin@gmail.com>
7 */
8#include <linux/suspend.h>
9#include <linux/interrupt.h>
10#include <linux/pm.h>
11
12#include <asm/i8259.h>
13#include <asm/mipsregs.h>
14
15#include <loongson.h>
16
17static unsigned int __maybe_unused cached_master_mask;	/* i8259A */
18static unsigned int __maybe_unused cached_slave_mask;
19static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
20
21void arch_suspend_disable_irqs(void)
22{
23	/* disable all mips events */
24	local_irq_disable();
25
26#ifdef CONFIG_I8259
27	/* disable all events of i8259A */
28	cached_slave_mask = inb(PIC_SLAVE_IMR);
29	cached_master_mask = inb(PIC_MASTER_IMR);
30
31	outb(0xff, PIC_SLAVE_IMR);
32	inb(PIC_SLAVE_IMR);
33	outb(0xff, PIC_MASTER_IMR);
34	inb(PIC_MASTER_IMR);
35#endif
36	/* disable all events of bonito */
37	cached_bonito_irq_mask = LOONGSON_INTEN;
38	LOONGSON_INTENCLR = 0xffff;
39	(void)LOONGSON_INTENCLR;
40}
41
42void arch_suspend_enable_irqs(void)
43{
44	/* enable all mips events */
45	local_irq_enable();
46#ifdef CONFIG_I8259
47	/* only enable the cached events of i8259A */
48	outb(cached_slave_mask, PIC_SLAVE_IMR);
49	outb(cached_master_mask, PIC_MASTER_IMR);
50#endif
51	/* enable all cached events of bonito */
52	LOONGSON_INTENSET = cached_bonito_irq_mask;
53	(void)LOONGSON_INTENSET;
54}
55
56/*
57 * Setup the board-specific events for waking up loongson from wait mode
58 */
59void __weak setup_wakeup_events(void)
60{
61}
62
63/*
64 * Check wakeup events
65 */
66int __weak wakeup_loongson(void)
67{
68	return 1;
69}
70
71/*
72 * If the events are really what we want to wakeup the CPU, wake it up
73 * otherwise put the CPU asleep again.
74 */
75static void wait_for_wakeup_events(void)
76{
77	while (!wakeup_loongson())
78		writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
79}
80
81/*
82 * Stop all perf counters
83 *
84 * $24 is the control register of Loongson perf counter
85 */
86static inline void stop_perf_counters(void)
87{
88	__write_64bit_c0_register($24, 0, 0);
89}
90
91
92static void loongson_suspend_enter(void)
93{
94	unsigned int cached_cpu_freq;
95
96	/* setup wakeup events via enabling the IRQs */
97	setup_wakeup_events();
98
99	stop_perf_counters();
100
101	cached_cpu_freq = readl(LOONGSON_CHIPCFG);
102
103	/* Put CPU into wait mode */
104	writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
105
106	/* wait for the given events to wakeup cpu from wait mode */
107	wait_for_wakeup_events();
108
109	writel(cached_cpu_freq, LOONGSON_CHIPCFG);
110
111	mmiowb();
112}
113
114void __weak mach_suspend(void)
115{
116}
117
118void __weak mach_resume(void)
119{
120}
121
122static int loongson_pm_enter(suspend_state_t state)
123{
124	mach_suspend();
125
126	/* processor specific suspend */
127	loongson_suspend_enter();
128
129	mach_resume();
130
131	return 0;
132}
133
134static int loongson_pm_valid_state(suspend_state_t state)
135{
136	switch (state) {
137	case PM_SUSPEND_ON:
138	case PM_SUSPEND_STANDBY:
139	case PM_SUSPEND_MEM:
140		return 1;
141
142	default:
143		return 0;
144	}
145}
146
147static const struct platform_suspend_ops loongson_pm_ops = {
148	.valid	= loongson_pm_valid_state,
149	.enter	= loongson_pm_enter,
150};
151
152static int __init loongson_pm_init(void)
153{
154	suspend_set_ops(&loongson_pm_ops);
155
156	return 0;
157}
158arch_initcall(loongson_pm_init);
159