1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* ********************************************************************* 3 * SB1250 Board Support Package 4 * 5 * LDT constants File: sb1250_ldt.h 6 * 7 * This module contains constants and macros to describe 8 * the LDT interface on the SB1250. 9 * 10 * SB1250 specification level: User's manual 1/02/02 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000, 2001, 2002, 2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 ********************************************************************* */ 18 19 20#ifndef _SB1250_LDT_H 21#define _SB1250_LDT_H 22 23#include <asm/sibyte/sb1250_defs.h> 24 25#define K_LDT_VENDOR_SIBYTE 0x166D 26#define K_LDT_DEVICE_SB1250 0x0002 27 28/* 29 * LDT Interface Type 1 (bridge) configuration header 30 */ 31 32#define R_LDT_TYPE1_DEVICEID 0x0000 33#define R_LDT_TYPE1_CMDSTATUS 0x0004 34#define R_LDT_TYPE1_CLASSREV 0x0008 35#define R_LDT_TYPE1_DEVHDR 0x000C 36#define R_LDT_TYPE1_BAR0 0x0010 /* not used */ 37#define R_LDT_TYPE1_BAR1 0x0014 /* not used */ 38 39#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */ 40#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */ 41#define R_LDT_TYPE1_MEMLIMIT 0x0020 42#define R_LDT_TYPE1_PREFETCH 0x0024 43#define R_LDT_TYPE1_PREF_BASE 0x0028 44#define R_LDT_TYPE1_PREF_LIMIT 0x002C 45#define R_LDT_TYPE1_IOLIMIT 0x0030 46#define R_LDT_TYPE1_CAPPTR 0x0034 47#define R_LDT_TYPE1_ROMADDR 0x0038 48#define R_LDT_TYPE1_BRCTL 0x003C 49#define R_LDT_TYPE1_CMD 0x0040 50#define R_LDT_TYPE1_LINKCTRL 0x0044 51#define R_LDT_TYPE1_LINKFREQ 0x0048 52#define R_LDT_TYPE1_RESERVED1 0x004C 53#define R_LDT_TYPE1_SRICMD 0x0050 54#define R_LDT_TYPE1_SRITXNUM 0x0054 55#define R_LDT_TYPE1_SRIRXNUM 0x0058 56#define R_LDT_TYPE1_ERRSTATUS 0x0068 57#define R_LDT_TYPE1_SRICTRL 0x006C 58#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 59#define R_LDT_TYPE1_ADDSTATUS 0x0070 60#endif /* 1250 PASS2 || 112x PASS1 */ 61#define R_LDT_TYPE1_TXBUFCNT 0x00C8 62#define R_LDT_TYPE1_EXPCRC 0x00DC 63#define R_LDT_TYPE1_RXCRC 0x00F0 64 65 66/* 67 * LDT Device ID register 68 */ 69 70#define S_LDT_DEVICEID_VENDOR 0 71#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) 72#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) 73#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) 74 75#define S_LDT_DEVICEID_DEVICEID 16 76#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) 77#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) 78#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) 79 80 81/* 82 * LDT Command Register (Table 8-13) 83 */ 84 85#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) 86#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) 87#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2) 88#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) 89#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) 90#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) 91#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6) 92#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7) 93#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8) 94#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) 95 96/* 97 * LDT class and revision registers 98 */ 99 100#define S_LDT_CLASSREV_REV 0 101#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) 102#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) 103#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) 104 105#define S_LDT_CLASSREV_CLASS 8 106#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) 107#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) 108#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) 109 110#define K_LDT_REV 0x01 111#define K_LDT_CLASS 0x060000 112 113/* 114 * Device Header (offset 0x0C) 115 */ 116 117#define S_LDT_DEVHDR_CLINESZ 0 118#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) 119#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) 120#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) 121 122#define S_LDT_DEVHDR_LATTMR 8 123#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) 124#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) 125#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) 126 127#define S_LDT_DEVHDR_HDRTYPE 16 128#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) 129#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) 130#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) 131 132#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 133 134#define S_LDT_DEVHDR_BIST 24 135#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) 136#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) 137#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) 138 139 140 141/* 142 * LDT Status Register (Table 8-14). Note that these constants 143 * assume you've read the command and status register 144 * together (32-bit read at offset 0x04) 145 * 146 * These bits also apply to the secondary status 147 * register (Table 8-15), offset 0x1C 148 */ 149 150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 151#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) 152#endif /* 1250 PASS2 || 112x PASS1 */ 153#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20) 154#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) 155#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) 156#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) 157#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) 158 159#define S_LDT_STATUS_DEVSELTIMING 25 160#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) 161#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) 162#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) 163 164#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) 165#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) 166#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) 167#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) 168#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) 169 170/* 171 * Bridge Control Register (Table 8-16). Note that these 172 * constants assume you've read the register as a 32-bit 173 * read (offset 0x3C) 174 */ 175 176#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16) 177#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17) 178#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18) 179#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19) 180#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21) 181#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22) 182#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23) 183#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24) 184#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25) 185#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26) 186#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27) 187 188/* 189 * LDT Command Register (Table 8-17). Note that these constants 190 * assume you've read the command and status register together 191 * 32-bit read at offset 0x40 192 */ 193 194#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16) 195#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) 196 197#define S_LDT_CMD_CAPTYPE 29 198#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) 199#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) 200#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) 201 202/* 203 * LDT link control register (Table 8-18), and (Table 8-19) 204 */ 205 206#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1) 207#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2) 208#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3) 209#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) 210#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5) 211#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6) 212#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) 213 214#define S_LDT_LINKCTRL_CRCERR 8 215#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) 216#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) 217#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) 218 219#define S_LDT_LINKCTRL_MAXIN 16 220#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) 221#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) 222#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) 223 224#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) 225 226#define S_LDT_LINKCTRL_MAXOUT 20 227#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) 228#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) 229#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) 230 231#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) 232 233#define S_LDT_LINKCTRL_WIDTHIN 24 234#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) 235#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) 236#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) 237 238#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) 239 240#define S_LDT_LINKCTRL_WIDTHOUT 28 241#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) 242#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) 243#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) 244 245#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) 246 247/* 248 * LDT Link frequency register (Table 8-20) offset 0x48 249 */ 250 251#define S_LDT_LINKFREQ_FREQ 8 252#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) 253#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) 254#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) 255 256#define K_LDT_LINKFREQ_200MHZ 0 257#define K_LDT_LINKFREQ_300MHZ 1 258#define K_LDT_LINKFREQ_400MHZ 2 259#define K_LDT_LINKFREQ_500MHZ 3 260#define K_LDT_LINKFREQ_600MHZ 4 261#define K_LDT_LINKFREQ_800MHZ 5 262#define K_LDT_LINKFREQ_1000MHZ 6 263 264/* 265 * LDT SRI Command Register (Table 8-21). Note that these constants 266 * assume you've read the command and status register together 267 * 32-bit read at offset 0x50 268 */ 269 270#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16) 271#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17) 272#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18) 273#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 274#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */ 275#endif /* up to 1250 PASS1 */ 276#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 277#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) 278#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) 279#endif /* 1250 PASS2 || 112x PASS1 */ 280 281 282#define S_LDT_SRICMD_RXMARGIN 20 283#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) 284#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) 285#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) 286 287#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) 288 289#define S_LDT_SRICMD_TXINITIALOFFSET 28 290#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) 291#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) 292#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) 293 294#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) 295 296/* 297 * LDT Error control and status register (Table 8-22) (Table 8-23) 298 */ 299 300#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0) 301#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1) 302#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2) 303#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3) 304#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4) 305#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) 306#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) 307#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) 308#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) 309#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) 310#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) 311#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) 312#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) 313#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) 314#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) 315#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) 316#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) 317#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) 318 319#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) 320#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) 321#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26) 322#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27) 323#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28) 324 325/* 326 * SRI Control register (Table 8-24, 8-25) Offset 0x6C 327 */ 328 329#define S_LDT_SRICTRL_NEEDRESP 0 330#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) 331#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) 332#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) 333 334#define S_LDT_SRICTRL_NEEDNPREQ 2 335#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) 336#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) 337#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) 338 339#define S_LDT_SRICTRL_NEEDPREQ 4 340#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) 341#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) 342#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) 343 344#define S_LDT_SRICTRL_WANTRESP 8 345#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) 346#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) 347#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) 348 349#define S_LDT_SRICTRL_WANTNPREQ 10 350#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) 351#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) 352#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) 353 354#define S_LDT_SRICTRL_WANTPREQ 12 355#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) 356#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) 357#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) 358 359#define S_LDT_SRICTRL_BUFRELSPACE 16 360#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) 361#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) 362#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) 363 364/* 365 * LDT SRI Transmit Buffer Count register (Table 8-26) 366 */ 367 368#define S_LDT_TXBUFCNT_PCMD 0 369#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) 370#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) 371#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) 372 373#define S_LDT_TXBUFCNT_PDATA 4 374#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) 375#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) 376#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) 377 378#define S_LDT_TXBUFCNT_NPCMD 8 379#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) 380#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) 381#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) 382 383#define S_LDT_TXBUFCNT_NPDATA 12 384#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) 385#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) 386#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) 387 388#define S_LDT_TXBUFCNT_RCMD 16 389#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) 390#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) 391#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) 392 393#define S_LDT_TXBUFCNT_RDATA 20 394#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) 395#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) 396#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) 397 398#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 399/* 400 * Additional Status Register 401 */ 402 403#define S_LDT_ADDSTATUS_TGTDONE 0 404#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) 405#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) 406#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) 407#endif /* 1250 PASS2 || 112x PASS1 */ 408 409#endif 410