1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_IPD_DEFS_H__ 29#define __CVMX_IPD_DEFS_H__ 30 31#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) 32#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) 33#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) 34#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) 35#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) 36#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) 37#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) 38#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) 39#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) 40#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) 41#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) 42#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) 43#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) 44#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) 45#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) 46#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) 47#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) 48#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) 49#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) 50#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) 51#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) 52#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) 53#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) 54#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) 55#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) 56#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) 57#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) 58#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) 59#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) 60#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) 61#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) 62#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) 63#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) 64#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) 65#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) 66#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) 67#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) 68#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) 69#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) 70#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) 71#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) 72#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) 73#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) 74#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) 75#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) 76#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) 77#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) 78#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) 79#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) 80#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) 81#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) 82#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) 83#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) 84#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) 85#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) 86#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) 87#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) 88#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) 89#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) 90#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) 91#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) 92#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) 93#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) 94#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) 95#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) 96#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) 97#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) 98#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) 99 100union cvmx_ipd_1st_mbuff_skip { 101 uint64_t u64; 102 struct cvmx_ipd_1st_mbuff_skip_s { 103#ifdef __BIG_ENDIAN_BITFIELD 104 uint64_t reserved_6_63:58; 105 uint64_t skip_sz:6; 106#else 107 uint64_t skip_sz:6; 108 uint64_t reserved_6_63:58; 109#endif 110 } s; 111}; 112 113union cvmx_ipd_1st_next_ptr_back { 114 uint64_t u64; 115 struct cvmx_ipd_1st_next_ptr_back_s { 116#ifdef __BIG_ENDIAN_BITFIELD 117 uint64_t reserved_4_63:60; 118 uint64_t back:4; 119#else 120 uint64_t back:4; 121 uint64_t reserved_4_63:60; 122#endif 123 } s; 124}; 125 126union cvmx_ipd_2nd_next_ptr_back { 127 uint64_t u64; 128 struct cvmx_ipd_2nd_next_ptr_back_s { 129#ifdef __BIG_ENDIAN_BITFIELD 130 uint64_t reserved_4_63:60; 131 uint64_t back:4; 132#else 133 uint64_t back:4; 134 uint64_t reserved_4_63:60; 135#endif 136 } s; 137}; 138 139union cvmx_ipd_bist_status { 140 uint64_t u64; 141 struct cvmx_ipd_bist_status_s { 142#ifdef __BIG_ENDIAN_BITFIELD 143 uint64_t reserved_23_63:41; 144 uint64_t iiwo1:1; 145 uint64_t iiwo0:1; 146 uint64_t iio1:1; 147 uint64_t iio0:1; 148 uint64_t pbm4:1; 149 uint64_t csr_mem:1; 150 uint64_t csr_ncmd:1; 151 uint64_t pwq_wqed:1; 152 uint64_t pwq_wp1:1; 153 uint64_t pwq_pow:1; 154 uint64_t ipq_pbe1:1; 155 uint64_t ipq_pbe0:1; 156 uint64_t pbm3:1; 157 uint64_t pbm2:1; 158 uint64_t pbm1:1; 159 uint64_t pbm0:1; 160 uint64_t pbm_word:1; 161 uint64_t pwq1:1; 162 uint64_t pwq0:1; 163 uint64_t prc_off:1; 164 uint64_t ipd_old:1; 165 uint64_t ipd_new:1; 166 uint64_t pwp:1; 167#else 168 uint64_t pwp:1; 169 uint64_t ipd_new:1; 170 uint64_t ipd_old:1; 171 uint64_t prc_off:1; 172 uint64_t pwq0:1; 173 uint64_t pwq1:1; 174 uint64_t pbm_word:1; 175 uint64_t pbm0:1; 176 uint64_t pbm1:1; 177 uint64_t pbm2:1; 178 uint64_t pbm3:1; 179 uint64_t ipq_pbe0:1; 180 uint64_t ipq_pbe1:1; 181 uint64_t pwq_pow:1; 182 uint64_t pwq_wp1:1; 183 uint64_t pwq_wqed:1; 184 uint64_t csr_ncmd:1; 185 uint64_t csr_mem:1; 186 uint64_t pbm4:1; 187 uint64_t iio0:1; 188 uint64_t iio1:1; 189 uint64_t iiwo0:1; 190 uint64_t iiwo1:1; 191 uint64_t reserved_23_63:41; 192#endif 193 } s; 194 struct cvmx_ipd_bist_status_cn30xx { 195#ifdef __BIG_ENDIAN_BITFIELD 196 uint64_t reserved_16_63:48; 197 uint64_t pwq_wqed:1; 198 uint64_t pwq_wp1:1; 199 uint64_t pwq_pow:1; 200 uint64_t ipq_pbe1:1; 201 uint64_t ipq_pbe0:1; 202 uint64_t pbm3:1; 203 uint64_t pbm2:1; 204 uint64_t pbm1:1; 205 uint64_t pbm0:1; 206 uint64_t pbm_word:1; 207 uint64_t pwq1:1; 208 uint64_t pwq0:1; 209 uint64_t prc_off:1; 210 uint64_t ipd_old:1; 211 uint64_t ipd_new:1; 212 uint64_t pwp:1; 213#else 214 uint64_t pwp:1; 215 uint64_t ipd_new:1; 216 uint64_t ipd_old:1; 217 uint64_t prc_off:1; 218 uint64_t pwq0:1; 219 uint64_t pwq1:1; 220 uint64_t pbm_word:1; 221 uint64_t pbm0:1; 222 uint64_t pbm1:1; 223 uint64_t pbm2:1; 224 uint64_t pbm3:1; 225 uint64_t ipq_pbe0:1; 226 uint64_t ipq_pbe1:1; 227 uint64_t pwq_pow:1; 228 uint64_t pwq_wp1:1; 229 uint64_t pwq_wqed:1; 230 uint64_t reserved_16_63:48; 231#endif 232 } cn30xx; 233 struct cvmx_ipd_bist_status_cn52xx { 234#ifdef __BIG_ENDIAN_BITFIELD 235 uint64_t reserved_18_63:46; 236 uint64_t csr_mem:1; 237 uint64_t csr_ncmd:1; 238 uint64_t pwq_wqed:1; 239 uint64_t pwq_wp1:1; 240 uint64_t pwq_pow:1; 241 uint64_t ipq_pbe1:1; 242 uint64_t ipq_pbe0:1; 243 uint64_t pbm3:1; 244 uint64_t pbm2:1; 245 uint64_t pbm1:1; 246 uint64_t pbm0:1; 247 uint64_t pbm_word:1; 248 uint64_t pwq1:1; 249 uint64_t pwq0:1; 250 uint64_t prc_off:1; 251 uint64_t ipd_old:1; 252 uint64_t ipd_new:1; 253 uint64_t pwp:1; 254#else 255 uint64_t pwp:1; 256 uint64_t ipd_new:1; 257 uint64_t ipd_old:1; 258 uint64_t prc_off:1; 259 uint64_t pwq0:1; 260 uint64_t pwq1:1; 261 uint64_t pbm_word:1; 262 uint64_t pbm0:1; 263 uint64_t pbm1:1; 264 uint64_t pbm2:1; 265 uint64_t pbm3:1; 266 uint64_t ipq_pbe0:1; 267 uint64_t ipq_pbe1:1; 268 uint64_t pwq_pow:1; 269 uint64_t pwq_wp1:1; 270 uint64_t pwq_wqed:1; 271 uint64_t csr_ncmd:1; 272 uint64_t csr_mem:1; 273 uint64_t reserved_18_63:46; 274#endif 275 } cn52xx; 276}; 277 278union cvmx_ipd_bp_prt_red_end { 279 uint64_t u64; 280 struct cvmx_ipd_bp_prt_red_end_s { 281#ifdef __BIG_ENDIAN_BITFIELD 282 uint64_t reserved_48_63:16; 283 uint64_t prt_enb:48; 284#else 285 uint64_t prt_enb:48; 286 uint64_t reserved_48_63:16; 287#endif 288 } s; 289 struct cvmx_ipd_bp_prt_red_end_cn30xx { 290#ifdef __BIG_ENDIAN_BITFIELD 291 uint64_t reserved_36_63:28; 292 uint64_t prt_enb:36; 293#else 294 uint64_t prt_enb:36; 295 uint64_t reserved_36_63:28; 296#endif 297 } cn30xx; 298 struct cvmx_ipd_bp_prt_red_end_cn52xx { 299#ifdef __BIG_ENDIAN_BITFIELD 300 uint64_t reserved_40_63:24; 301 uint64_t prt_enb:40; 302#else 303 uint64_t prt_enb:40; 304 uint64_t reserved_40_63:24; 305#endif 306 } cn52xx; 307 struct cvmx_ipd_bp_prt_red_end_cn63xx { 308#ifdef __BIG_ENDIAN_BITFIELD 309 uint64_t reserved_44_63:20; 310 uint64_t prt_enb:44; 311#else 312 uint64_t prt_enb:44; 313 uint64_t reserved_44_63:20; 314#endif 315 } cn63xx; 316}; 317 318union cvmx_ipd_bpidx_mbuf_th { 319 uint64_t u64; 320 struct cvmx_ipd_bpidx_mbuf_th_s { 321#ifdef __BIG_ENDIAN_BITFIELD 322 uint64_t reserved_18_63:46; 323 uint64_t bp_enb:1; 324 uint64_t page_cnt:17; 325#else 326 uint64_t page_cnt:17; 327 uint64_t bp_enb:1; 328 uint64_t reserved_18_63:46; 329#endif 330 } s; 331}; 332 333union cvmx_ipd_bpid_bp_counterx { 334 uint64_t u64; 335 struct cvmx_ipd_bpid_bp_counterx_s { 336#ifdef __BIG_ENDIAN_BITFIELD 337 uint64_t reserved_25_63:39; 338 uint64_t cnt_val:25; 339#else 340 uint64_t cnt_val:25; 341 uint64_t reserved_25_63:39; 342#endif 343 } s; 344}; 345 346union cvmx_ipd_clk_count { 347 uint64_t u64; 348 struct cvmx_ipd_clk_count_s { 349#ifdef __BIG_ENDIAN_BITFIELD 350 uint64_t clk_cnt:64; 351#else 352 uint64_t clk_cnt:64; 353#endif 354 } s; 355}; 356 357union cvmx_ipd_credits { 358 uint64_t u64; 359 struct cvmx_ipd_credits_s { 360#ifdef __BIG_ENDIAN_BITFIELD 361 uint64_t reserved_16_63:48; 362 uint64_t iob_wrc:8; 363 uint64_t iob_wr:8; 364#else 365 uint64_t iob_wr:8; 366 uint64_t iob_wrc:8; 367 uint64_t reserved_16_63:48; 368#endif 369 } s; 370}; 371 372union cvmx_ipd_ctl_status { 373 uint64_t u64; 374 struct cvmx_ipd_ctl_status_s { 375#ifdef __BIG_ENDIAN_BITFIELD 376 uint64_t reserved_18_63:46; 377 uint64_t use_sop:1; 378 uint64_t rst_done:1; 379 uint64_t clken:1; 380 uint64_t no_wptr:1; 381 uint64_t pq_apkt:1; 382 uint64_t pq_nabuf:1; 383 uint64_t ipd_full:1; 384 uint64_t pkt_off:1; 385 uint64_t len_m8:1; 386 uint64_t reset:1; 387 uint64_t addpkt:1; 388 uint64_t naddbuf:1; 389 uint64_t pkt_lend:1; 390 uint64_t wqe_lend:1; 391 uint64_t pbp_en:1; 392 uint64_t opc_mode:2; 393 uint64_t ipd_en:1; 394#else 395 uint64_t ipd_en:1; 396 uint64_t opc_mode:2; 397 uint64_t pbp_en:1; 398 uint64_t wqe_lend:1; 399 uint64_t pkt_lend:1; 400 uint64_t naddbuf:1; 401 uint64_t addpkt:1; 402 uint64_t reset:1; 403 uint64_t len_m8:1; 404 uint64_t pkt_off:1; 405 uint64_t ipd_full:1; 406 uint64_t pq_nabuf:1; 407 uint64_t pq_apkt:1; 408 uint64_t no_wptr:1; 409 uint64_t clken:1; 410 uint64_t rst_done:1; 411 uint64_t use_sop:1; 412 uint64_t reserved_18_63:46; 413#endif 414 } s; 415 struct cvmx_ipd_ctl_status_cn30xx { 416#ifdef __BIG_ENDIAN_BITFIELD 417 uint64_t reserved_10_63:54; 418 uint64_t len_m8:1; 419 uint64_t reset:1; 420 uint64_t addpkt:1; 421 uint64_t naddbuf:1; 422 uint64_t pkt_lend:1; 423 uint64_t wqe_lend:1; 424 uint64_t pbp_en:1; 425 uint64_t opc_mode:2; 426 uint64_t ipd_en:1; 427#else 428 uint64_t ipd_en:1; 429 uint64_t opc_mode:2; 430 uint64_t pbp_en:1; 431 uint64_t wqe_lend:1; 432 uint64_t pkt_lend:1; 433 uint64_t naddbuf:1; 434 uint64_t addpkt:1; 435 uint64_t reset:1; 436 uint64_t len_m8:1; 437 uint64_t reserved_10_63:54; 438#endif 439 } cn30xx; 440 struct cvmx_ipd_ctl_status_cn38xxp2 { 441#ifdef __BIG_ENDIAN_BITFIELD 442 uint64_t reserved_9_63:55; 443 uint64_t reset:1; 444 uint64_t addpkt:1; 445 uint64_t naddbuf:1; 446 uint64_t pkt_lend:1; 447 uint64_t wqe_lend:1; 448 uint64_t pbp_en:1; 449 uint64_t opc_mode:2; 450 uint64_t ipd_en:1; 451#else 452 uint64_t ipd_en:1; 453 uint64_t opc_mode:2; 454 uint64_t pbp_en:1; 455 uint64_t wqe_lend:1; 456 uint64_t pkt_lend:1; 457 uint64_t naddbuf:1; 458 uint64_t addpkt:1; 459 uint64_t reset:1; 460 uint64_t reserved_9_63:55; 461#endif 462 } cn38xxp2; 463 struct cvmx_ipd_ctl_status_cn50xx { 464#ifdef __BIG_ENDIAN_BITFIELD 465 uint64_t reserved_15_63:49; 466 uint64_t no_wptr:1; 467 uint64_t pq_apkt:1; 468 uint64_t pq_nabuf:1; 469 uint64_t ipd_full:1; 470 uint64_t pkt_off:1; 471 uint64_t len_m8:1; 472 uint64_t reset:1; 473 uint64_t addpkt:1; 474 uint64_t naddbuf:1; 475 uint64_t pkt_lend:1; 476 uint64_t wqe_lend:1; 477 uint64_t pbp_en:1; 478 uint64_t opc_mode:2; 479 uint64_t ipd_en:1; 480#else 481 uint64_t ipd_en:1; 482 uint64_t opc_mode:2; 483 uint64_t pbp_en:1; 484 uint64_t wqe_lend:1; 485 uint64_t pkt_lend:1; 486 uint64_t naddbuf:1; 487 uint64_t addpkt:1; 488 uint64_t reset:1; 489 uint64_t len_m8:1; 490 uint64_t pkt_off:1; 491 uint64_t ipd_full:1; 492 uint64_t pq_nabuf:1; 493 uint64_t pq_apkt:1; 494 uint64_t no_wptr:1; 495 uint64_t reserved_15_63:49; 496#endif 497 } cn50xx; 498 struct cvmx_ipd_ctl_status_cn58xx { 499#ifdef __BIG_ENDIAN_BITFIELD 500 uint64_t reserved_12_63:52; 501 uint64_t ipd_full:1; 502 uint64_t pkt_off:1; 503 uint64_t len_m8:1; 504 uint64_t reset:1; 505 uint64_t addpkt:1; 506 uint64_t naddbuf:1; 507 uint64_t pkt_lend:1; 508 uint64_t wqe_lend:1; 509 uint64_t pbp_en:1; 510 uint64_t opc_mode:2; 511 uint64_t ipd_en:1; 512#else 513 uint64_t ipd_en:1; 514 uint64_t opc_mode:2; 515 uint64_t pbp_en:1; 516 uint64_t wqe_lend:1; 517 uint64_t pkt_lend:1; 518 uint64_t naddbuf:1; 519 uint64_t addpkt:1; 520 uint64_t reset:1; 521 uint64_t len_m8:1; 522 uint64_t pkt_off:1; 523 uint64_t ipd_full:1; 524 uint64_t reserved_12_63:52; 525#endif 526 } cn58xx; 527 struct cvmx_ipd_ctl_status_cn63xxp1 { 528#ifdef __BIG_ENDIAN_BITFIELD 529 uint64_t reserved_16_63:48; 530 uint64_t clken:1; 531 uint64_t no_wptr:1; 532 uint64_t pq_apkt:1; 533 uint64_t pq_nabuf:1; 534 uint64_t ipd_full:1; 535 uint64_t pkt_off:1; 536 uint64_t len_m8:1; 537 uint64_t reset:1; 538 uint64_t addpkt:1; 539 uint64_t naddbuf:1; 540 uint64_t pkt_lend:1; 541 uint64_t wqe_lend:1; 542 uint64_t pbp_en:1; 543 uint64_t opc_mode:2; 544 uint64_t ipd_en:1; 545#else 546 uint64_t ipd_en:1; 547 uint64_t opc_mode:2; 548 uint64_t pbp_en:1; 549 uint64_t wqe_lend:1; 550 uint64_t pkt_lend:1; 551 uint64_t naddbuf:1; 552 uint64_t addpkt:1; 553 uint64_t reset:1; 554 uint64_t len_m8:1; 555 uint64_t pkt_off:1; 556 uint64_t ipd_full:1; 557 uint64_t pq_nabuf:1; 558 uint64_t pq_apkt:1; 559 uint64_t no_wptr:1; 560 uint64_t clken:1; 561 uint64_t reserved_16_63:48; 562#endif 563 } cn63xxp1; 564}; 565 566union cvmx_ipd_ecc_ctl { 567 uint64_t u64; 568 struct cvmx_ipd_ecc_ctl_s { 569#ifdef __BIG_ENDIAN_BITFIELD 570 uint64_t reserved_8_63:56; 571 uint64_t pm3_syn:2; 572 uint64_t pm2_syn:2; 573 uint64_t pm1_syn:2; 574 uint64_t pm0_syn:2; 575#else 576 uint64_t pm0_syn:2; 577 uint64_t pm1_syn:2; 578 uint64_t pm2_syn:2; 579 uint64_t pm3_syn:2; 580 uint64_t reserved_8_63:56; 581#endif 582 } s; 583}; 584 585union cvmx_ipd_free_ptr_fifo_ctl { 586 uint64_t u64; 587 struct cvmx_ipd_free_ptr_fifo_ctl_s { 588#ifdef __BIG_ENDIAN_BITFIELD 589 uint64_t reserved_32_63:32; 590 uint64_t max_cnts:7; 591 uint64_t wraddr:8; 592 uint64_t praddr:8; 593 uint64_t cena:1; 594 uint64_t raddr:8; 595#else 596 uint64_t raddr:8; 597 uint64_t cena:1; 598 uint64_t praddr:8; 599 uint64_t wraddr:8; 600 uint64_t max_cnts:7; 601 uint64_t reserved_32_63:32; 602#endif 603 } s; 604}; 605 606union cvmx_ipd_free_ptr_value { 607 uint64_t u64; 608 struct cvmx_ipd_free_ptr_value_s { 609#ifdef __BIG_ENDIAN_BITFIELD 610 uint64_t reserved_33_63:31; 611 uint64_t ptr:33; 612#else 613 uint64_t ptr:33; 614 uint64_t reserved_33_63:31; 615#endif 616 } s; 617}; 618 619union cvmx_ipd_hold_ptr_fifo_ctl { 620 uint64_t u64; 621 struct cvmx_ipd_hold_ptr_fifo_ctl_s { 622#ifdef __BIG_ENDIAN_BITFIELD 623 uint64_t reserved_43_63:21; 624 uint64_t ptr:33; 625 uint64_t max_pkt:3; 626 uint64_t praddr:3; 627 uint64_t cena:1; 628 uint64_t raddr:3; 629#else 630 uint64_t raddr:3; 631 uint64_t cena:1; 632 uint64_t praddr:3; 633 uint64_t max_pkt:3; 634 uint64_t ptr:33; 635 uint64_t reserved_43_63:21; 636#endif 637 } s; 638}; 639 640union cvmx_ipd_int_enb { 641 uint64_t u64; 642 struct cvmx_ipd_int_enb_s { 643#ifdef __BIG_ENDIAN_BITFIELD 644 uint64_t reserved_23_63:41; 645 uint64_t pw3_dbe:1; 646 uint64_t pw3_sbe:1; 647 uint64_t pw2_dbe:1; 648 uint64_t pw2_sbe:1; 649 uint64_t pw1_dbe:1; 650 uint64_t pw1_sbe:1; 651 uint64_t pw0_dbe:1; 652 uint64_t pw0_sbe:1; 653 uint64_t dat:1; 654 uint64_t eop:1; 655 uint64_t sop:1; 656 uint64_t pq_sub:1; 657 uint64_t pq_add:1; 658 uint64_t bc_ovr:1; 659 uint64_t d_coll:1; 660 uint64_t c_coll:1; 661 uint64_t cc_ovr:1; 662 uint64_t dc_ovr:1; 663 uint64_t bp_sub:1; 664 uint64_t prc_par3:1; 665 uint64_t prc_par2:1; 666 uint64_t prc_par1:1; 667 uint64_t prc_par0:1; 668#else 669 uint64_t prc_par0:1; 670 uint64_t prc_par1:1; 671 uint64_t prc_par2:1; 672 uint64_t prc_par3:1; 673 uint64_t bp_sub:1; 674 uint64_t dc_ovr:1; 675 uint64_t cc_ovr:1; 676 uint64_t c_coll:1; 677 uint64_t d_coll:1; 678 uint64_t bc_ovr:1; 679 uint64_t pq_add:1; 680 uint64_t pq_sub:1; 681 uint64_t sop:1; 682 uint64_t eop:1; 683 uint64_t dat:1; 684 uint64_t pw0_sbe:1; 685 uint64_t pw0_dbe:1; 686 uint64_t pw1_sbe:1; 687 uint64_t pw1_dbe:1; 688 uint64_t pw2_sbe:1; 689 uint64_t pw2_dbe:1; 690 uint64_t pw3_sbe:1; 691 uint64_t pw3_dbe:1; 692 uint64_t reserved_23_63:41; 693#endif 694 } s; 695 struct cvmx_ipd_int_enb_cn30xx { 696#ifdef __BIG_ENDIAN_BITFIELD 697 uint64_t reserved_5_63:59; 698 uint64_t bp_sub:1; 699 uint64_t prc_par3:1; 700 uint64_t prc_par2:1; 701 uint64_t prc_par1:1; 702 uint64_t prc_par0:1; 703#else 704 uint64_t prc_par0:1; 705 uint64_t prc_par1:1; 706 uint64_t prc_par2:1; 707 uint64_t prc_par3:1; 708 uint64_t bp_sub:1; 709 uint64_t reserved_5_63:59; 710#endif 711 } cn30xx; 712 struct cvmx_ipd_int_enb_cn38xx { 713#ifdef __BIG_ENDIAN_BITFIELD 714 uint64_t reserved_10_63:54; 715 uint64_t bc_ovr:1; 716 uint64_t d_coll:1; 717 uint64_t c_coll:1; 718 uint64_t cc_ovr:1; 719 uint64_t dc_ovr:1; 720 uint64_t bp_sub:1; 721 uint64_t prc_par3:1; 722 uint64_t prc_par2:1; 723 uint64_t prc_par1:1; 724 uint64_t prc_par0:1; 725#else 726 uint64_t prc_par0:1; 727 uint64_t prc_par1:1; 728 uint64_t prc_par2:1; 729 uint64_t prc_par3:1; 730 uint64_t bp_sub:1; 731 uint64_t dc_ovr:1; 732 uint64_t cc_ovr:1; 733 uint64_t c_coll:1; 734 uint64_t d_coll:1; 735 uint64_t bc_ovr:1; 736 uint64_t reserved_10_63:54; 737#endif 738 } cn38xx; 739 struct cvmx_ipd_int_enb_cn52xx { 740#ifdef __BIG_ENDIAN_BITFIELD 741 uint64_t reserved_12_63:52; 742 uint64_t pq_sub:1; 743 uint64_t pq_add:1; 744 uint64_t bc_ovr:1; 745 uint64_t d_coll:1; 746 uint64_t c_coll:1; 747 uint64_t cc_ovr:1; 748 uint64_t dc_ovr:1; 749 uint64_t bp_sub:1; 750 uint64_t prc_par3:1; 751 uint64_t prc_par2:1; 752 uint64_t prc_par1:1; 753 uint64_t prc_par0:1; 754#else 755 uint64_t prc_par0:1; 756 uint64_t prc_par1:1; 757 uint64_t prc_par2:1; 758 uint64_t prc_par3:1; 759 uint64_t bp_sub:1; 760 uint64_t dc_ovr:1; 761 uint64_t cc_ovr:1; 762 uint64_t c_coll:1; 763 uint64_t d_coll:1; 764 uint64_t bc_ovr:1; 765 uint64_t pq_add:1; 766 uint64_t pq_sub:1; 767 uint64_t reserved_12_63:52; 768#endif 769 } cn52xx; 770}; 771 772union cvmx_ipd_int_sum { 773 uint64_t u64; 774 struct cvmx_ipd_int_sum_s { 775#ifdef __BIG_ENDIAN_BITFIELD 776 uint64_t reserved_23_63:41; 777 uint64_t pw3_dbe:1; 778 uint64_t pw3_sbe:1; 779 uint64_t pw2_dbe:1; 780 uint64_t pw2_sbe:1; 781 uint64_t pw1_dbe:1; 782 uint64_t pw1_sbe:1; 783 uint64_t pw0_dbe:1; 784 uint64_t pw0_sbe:1; 785 uint64_t dat:1; 786 uint64_t eop:1; 787 uint64_t sop:1; 788 uint64_t pq_sub:1; 789 uint64_t pq_add:1; 790 uint64_t bc_ovr:1; 791 uint64_t d_coll:1; 792 uint64_t c_coll:1; 793 uint64_t cc_ovr:1; 794 uint64_t dc_ovr:1; 795 uint64_t bp_sub:1; 796 uint64_t prc_par3:1; 797 uint64_t prc_par2:1; 798 uint64_t prc_par1:1; 799 uint64_t prc_par0:1; 800#else 801 uint64_t prc_par0:1; 802 uint64_t prc_par1:1; 803 uint64_t prc_par2:1; 804 uint64_t prc_par3:1; 805 uint64_t bp_sub:1; 806 uint64_t dc_ovr:1; 807 uint64_t cc_ovr:1; 808 uint64_t c_coll:1; 809 uint64_t d_coll:1; 810 uint64_t bc_ovr:1; 811 uint64_t pq_add:1; 812 uint64_t pq_sub:1; 813 uint64_t sop:1; 814 uint64_t eop:1; 815 uint64_t dat:1; 816 uint64_t pw0_sbe:1; 817 uint64_t pw0_dbe:1; 818 uint64_t pw1_sbe:1; 819 uint64_t pw1_dbe:1; 820 uint64_t pw2_sbe:1; 821 uint64_t pw2_dbe:1; 822 uint64_t pw3_sbe:1; 823 uint64_t pw3_dbe:1; 824 uint64_t reserved_23_63:41; 825#endif 826 } s; 827 struct cvmx_ipd_int_sum_cn30xx { 828#ifdef __BIG_ENDIAN_BITFIELD 829 uint64_t reserved_5_63:59; 830 uint64_t bp_sub:1; 831 uint64_t prc_par3:1; 832 uint64_t prc_par2:1; 833 uint64_t prc_par1:1; 834 uint64_t prc_par0:1; 835#else 836 uint64_t prc_par0:1; 837 uint64_t prc_par1:1; 838 uint64_t prc_par2:1; 839 uint64_t prc_par3:1; 840 uint64_t bp_sub:1; 841 uint64_t reserved_5_63:59; 842#endif 843 } cn30xx; 844 struct cvmx_ipd_int_sum_cn38xx { 845#ifdef __BIG_ENDIAN_BITFIELD 846 uint64_t reserved_10_63:54; 847 uint64_t bc_ovr:1; 848 uint64_t d_coll:1; 849 uint64_t c_coll:1; 850 uint64_t cc_ovr:1; 851 uint64_t dc_ovr:1; 852 uint64_t bp_sub:1; 853 uint64_t prc_par3:1; 854 uint64_t prc_par2:1; 855 uint64_t prc_par1:1; 856 uint64_t prc_par0:1; 857#else 858 uint64_t prc_par0:1; 859 uint64_t prc_par1:1; 860 uint64_t prc_par2:1; 861 uint64_t prc_par3:1; 862 uint64_t bp_sub:1; 863 uint64_t dc_ovr:1; 864 uint64_t cc_ovr:1; 865 uint64_t c_coll:1; 866 uint64_t d_coll:1; 867 uint64_t bc_ovr:1; 868 uint64_t reserved_10_63:54; 869#endif 870 } cn38xx; 871 struct cvmx_ipd_int_sum_cn52xx { 872#ifdef __BIG_ENDIAN_BITFIELD 873 uint64_t reserved_12_63:52; 874 uint64_t pq_sub:1; 875 uint64_t pq_add:1; 876 uint64_t bc_ovr:1; 877 uint64_t d_coll:1; 878 uint64_t c_coll:1; 879 uint64_t cc_ovr:1; 880 uint64_t dc_ovr:1; 881 uint64_t bp_sub:1; 882 uint64_t prc_par3:1; 883 uint64_t prc_par2:1; 884 uint64_t prc_par1:1; 885 uint64_t prc_par0:1; 886#else 887 uint64_t prc_par0:1; 888 uint64_t prc_par1:1; 889 uint64_t prc_par2:1; 890 uint64_t prc_par3:1; 891 uint64_t bp_sub:1; 892 uint64_t dc_ovr:1; 893 uint64_t cc_ovr:1; 894 uint64_t c_coll:1; 895 uint64_t d_coll:1; 896 uint64_t bc_ovr:1; 897 uint64_t pq_add:1; 898 uint64_t pq_sub:1; 899 uint64_t reserved_12_63:52; 900#endif 901 } cn52xx; 902}; 903 904union cvmx_ipd_next_pkt_ptr { 905 uint64_t u64; 906 struct cvmx_ipd_next_pkt_ptr_s { 907#ifdef __BIG_ENDIAN_BITFIELD 908 uint64_t reserved_33_63:31; 909 uint64_t ptr:33; 910#else 911 uint64_t ptr:33; 912 uint64_t reserved_33_63:31; 913#endif 914 } s; 915}; 916 917union cvmx_ipd_next_wqe_ptr { 918 uint64_t u64; 919 struct cvmx_ipd_next_wqe_ptr_s { 920#ifdef __BIG_ENDIAN_BITFIELD 921 uint64_t reserved_33_63:31; 922 uint64_t ptr:33; 923#else 924 uint64_t ptr:33; 925 uint64_t reserved_33_63:31; 926#endif 927 } s; 928}; 929 930union cvmx_ipd_not_1st_mbuff_skip { 931 uint64_t u64; 932 struct cvmx_ipd_not_1st_mbuff_skip_s { 933#ifdef __BIG_ENDIAN_BITFIELD 934 uint64_t reserved_6_63:58; 935 uint64_t skip_sz:6; 936#else 937 uint64_t skip_sz:6; 938 uint64_t reserved_6_63:58; 939#endif 940 } s; 941}; 942 943union cvmx_ipd_on_bp_drop_pktx { 944 uint64_t u64; 945 struct cvmx_ipd_on_bp_drop_pktx_s { 946#ifdef __BIG_ENDIAN_BITFIELD 947 uint64_t prt_enb:64; 948#else 949 uint64_t prt_enb:64; 950#endif 951 } s; 952}; 953 954union cvmx_ipd_packet_mbuff_size { 955 uint64_t u64; 956 struct cvmx_ipd_packet_mbuff_size_s { 957#ifdef __BIG_ENDIAN_BITFIELD 958 uint64_t reserved_12_63:52; 959 uint64_t mb_size:12; 960#else 961 uint64_t mb_size:12; 962 uint64_t reserved_12_63:52; 963#endif 964 } s; 965}; 966 967union cvmx_ipd_pkt_err { 968 uint64_t u64; 969 struct cvmx_ipd_pkt_err_s { 970#ifdef __BIG_ENDIAN_BITFIELD 971 uint64_t reserved_6_63:58; 972 uint64_t reasm:6; 973#else 974 uint64_t reasm:6; 975 uint64_t reserved_6_63:58; 976#endif 977 } s; 978}; 979 980union cvmx_ipd_pkt_ptr_valid { 981 uint64_t u64; 982 struct cvmx_ipd_pkt_ptr_valid_s { 983#ifdef __BIG_ENDIAN_BITFIELD 984 uint64_t reserved_29_63:35; 985 uint64_t ptr:29; 986#else 987 uint64_t ptr:29; 988 uint64_t reserved_29_63:35; 989#endif 990 } s; 991}; 992 993union cvmx_ipd_portx_bp_page_cnt { 994 uint64_t u64; 995 struct cvmx_ipd_portx_bp_page_cnt_s { 996#ifdef __BIG_ENDIAN_BITFIELD 997 uint64_t reserved_18_63:46; 998 uint64_t bp_enb:1; 999 uint64_t page_cnt:17; 1000#else 1001 uint64_t page_cnt:17; 1002 uint64_t bp_enb:1; 1003 uint64_t reserved_18_63:46; 1004#endif 1005 } s; 1006}; 1007 1008union cvmx_ipd_portx_bp_page_cnt2 { 1009 uint64_t u64; 1010 struct cvmx_ipd_portx_bp_page_cnt2_s { 1011#ifdef __BIG_ENDIAN_BITFIELD 1012 uint64_t reserved_18_63:46; 1013 uint64_t bp_enb:1; 1014 uint64_t page_cnt:17; 1015#else 1016 uint64_t page_cnt:17; 1017 uint64_t bp_enb:1; 1018 uint64_t reserved_18_63:46; 1019#endif 1020 } s; 1021}; 1022 1023union cvmx_ipd_portx_bp_page_cnt3 { 1024 uint64_t u64; 1025 struct cvmx_ipd_portx_bp_page_cnt3_s { 1026#ifdef __BIG_ENDIAN_BITFIELD 1027 uint64_t reserved_18_63:46; 1028 uint64_t bp_enb:1; 1029 uint64_t page_cnt:17; 1030#else 1031 uint64_t page_cnt:17; 1032 uint64_t bp_enb:1; 1033 uint64_t reserved_18_63:46; 1034#endif 1035 } s; 1036}; 1037 1038union cvmx_ipd_port_bp_counters2_pairx { 1039 uint64_t u64; 1040 struct cvmx_ipd_port_bp_counters2_pairx_s { 1041#ifdef __BIG_ENDIAN_BITFIELD 1042 uint64_t reserved_25_63:39; 1043 uint64_t cnt_val:25; 1044#else 1045 uint64_t cnt_val:25; 1046 uint64_t reserved_25_63:39; 1047#endif 1048 } s; 1049}; 1050 1051union cvmx_ipd_port_bp_counters3_pairx { 1052 uint64_t u64; 1053 struct cvmx_ipd_port_bp_counters3_pairx_s { 1054#ifdef __BIG_ENDIAN_BITFIELD 1055 uint64_t reserved_25_63:39; 1056 uint64_t cnt_val:25; 1057#else 1058 uint64_t cnt_val:25; 1059 uint64_t reserved_25_63:39; 1060#endif 1061 } s; 1062}; 1063 1064union cvmx_ipd_port_bp_counters4_pairx { 1065 uint64_t u64; 1066 struct cvmx_ipd_port_bp_counters4_pairx_s { 1067#ifdef __BIG_ENDIAN_BITFIELD 1068 uint64_t reserved_25_63:39; 1069 uint64_t cnt_val:25; 1070#else 1071 uint64_t cnt_val:25; 1072 uint64_t reserved_25_63:39; 1073#endif 1074 } s; 1075}; 1076 1077union cvmx_ipd_port_bp_counters_pairx { 1078 uint64_t u64; 1079 struct cvmx_ipd_port_bp_counters_pairx_s { 1080#ifdef __BIG_ENDIAN_BITFIELD 1081 uint64_t reserved_25_63:39; 1082 uint64_t cnt_val:25; 1083#else 1084 uint64_t cnt_val:25; 1085 uint64_t reserved_25_63:39; 1086#endif 1087 } s; 1088}; 1089 1090union cvmx_ipd_port_ptr_fifo_ctl { 1091 uint64_t u64; 1092 struct cvmx_ipd_port_ptr_fifo_ctl_s { 1093#ifdef __BIG_ENDIAN_BITFIELD 1094 uint64_t reserved_48_63:16; 1095 uint64_t ptr:33; 1096 uint64_t max_pkt:7; 1097 uint64_t cena:1; 1098 uint64_t raddr:7; 1099#else 1100 uint64_t raddr:7; 1101 uint64_t cena:1; 1102 uint64_t max_pkt:7; 1103 uint64_t ptr:33; 1104 uint64_t reserved_48_63:16; 1105#endif 1106 } s; 1107}; 1108 1109union cvmx_ipd_port_qos_x_cnt { 1110 uint64_t u64; 1111 struct cvmx_ipd_port_qos_x_cnt_s { 1112#ifdef __BIG_ENDIAN_BITFIELD 1113 uint64_t wmark:32; 1114 uint64_t cnt:32; 1115#else 1116 uint64_t cnt:32; 1117 uint64_t wmark:32; 1118#endif 1119 } s; 1120}; 1121 1122union cvmx_ipd_port_qos_intx { 1123 uint64_t u64; 1124 struct cvmx_ipd_port_qos_intx_s { 1125#ifdef __BIG_ENDIAN_BITFIELD 1126 uint64_t intr:64; 1127#else 1128 uint64_t intr:64; 1129#endif 1130 } s; 1131}; 1132 1133union cvmx_ipd_port_qos_int_enbx { 1134 uint64_t u64; 1135 struct cvmx_ipd_port_qos_int_enbx_s { 1136#ifdef __BIG_ENDIAN_BITFIELD 1137 uint64_t enb:64; 1138#else 1139 uint64_t enb:64; 1140#endif 1141 } s; 1142}; 1143 1144union cvmx_ipd_port_sopx { 1145 uint64_t u64; 1146 struct cvmx_ipd_port_sopx_s { 1147#ifdef __BIG_ENDIAN_BITFIELD 1148 uint64_t sop:64; 1149#else 1150 uint64_t sop:64; 1151#endif 1152 } s; 1153}; 1154 1155union cvmx_ipd_prc_hold_ptr_fifo_ctl { 1156 uint64_t u64; 1157 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { 1158#ifdef __BIG_ENDIAN_BITFIELD 1159 uint64_t reserved_39_63:25; 1160 uint64_t max_pkt:3; 1161 uint64_t praddr:3; 1162 uint64_t ptr:29; 1163 uint64_t cena:1; 1164 uint64_t raddr:3; 1165#else 1166 uint64_t raddr:3; 1167 uint64_t cena:1; 1168 uint64_t ptr:29; 1169 uint64_t praddr:3; 1170 uint64_t max_pkt:3; 1171 uint64_t reserved_39_63:25; 1172#endif 1173 } s; 1174}; 1175 1176union cvmx_ipd_prc_port_ptr_fifo_ctl { 1177 uint64_t u64; 1178 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { 1179#ifdef __BIG_ENDIAN_BITFIELD 1180 uint64_t reserved_44_63:20; 1181 uint64_t max_pkt:7; 1182 uint64_t ptr:29; 1183 uint64_t cena:1; 1184 uint64_t raddr:7; 1185#else 1186 uint64_t raddr:7; 1187 uint64_t cena:1; 1188 uint64_t ptr:29; 1189 uint64_t max_pkt:7; 1190 uint64_t reserved_44_63:20; 1191#endif 1192 } s; 1193}; 1194 1195union cvmx_ipd_ptr_count { 1196 uint64_t u64; 1197 struct cvmx_ipd_ptr_count_s { 1198#ifdef __BIG_ENDIAN_BITFIELD 1199 uint64_t reserved_19_63:45; 1200 uint64_t pktv_cnt:1; 1201 uint64_t wqev_cnt:1; 1202 uint64_t pfif_cnt:3; 1203 uint64_t pkt_pcnt:7; 1204 uint64_t wqe_pcnt:7; 1205#else 1206 uint64_t wqe_pcnt:7; 1207 uint64_t pkt_pcnt:7; 1208 uint64_t pfif_cnt:3; 1209 uint64_t wqev_cnt:1; 1210 uint64_t pktv_cnt:1; 1211 uint64_t reserved_19_63:45; 1212#endif 1213 } s; 1214}; 1215 1216union cvmx_ipd_pwp_ptr_fifo_ctl { 1217 uint64_t u64; 1218 struct cvmx_ipd_pwp_ptr_fifo_ctl_s { 1219#ifdef __BIG_ENDIAN_BITFIELD 1220 uint64_t reserved_61_63:3; 1221 uint64_t max_cnts:7; 1222 uint64_t wraddr:8; 1223 uint64_t praddr:8; 1224 uint64_t ptr:29; 1225 uint64_t cena:1; 1226 uint64_t raddr:8; 1227#else 1228 uint64_t raddr:8; 1229 uint64_t cena:1; 1230 uint64_t ptr:29; 1231 uint64_t praddr:8; 1232 uint64_t wraddr:8; 1233 uint64_t max_cnts:7; 1234 uint64_t reserved_61_63:3; 1235#endif 1236 } s; 1237}; 1238 1239union cvmx_ipd_qosx_red_marks { 1240 uint64_t u64; 1241 struct cvmx_ipd_qosx_red_marks_s { 1242#ifdef __BIG_ENDIAN_BITFIELD 1243 uint64_t drop:32; 1244 uint64_t pass:32; 1245#else 1246 uint64_t pass:32; 1247 uint64_t drop:32; 1248#endif 1249 } s; 1250}; 1251 1252union cvmx_ipd_que0_free_page_cnt { 1253 uint64_t u64; 1254 struct cvmx_ipd_que0_free_page_cnt_s { 1255#ifdef __BIG_ENDIAN_BITFIELD 1256 uint64_t reserved_32_63:32; 1257 uint64_t q0_pcnt:32; 1258#else 1259 uint64_t q0_pcnt:32; 1260 uint64_t reserved_32_63:32; 1261#endif 1262 } s; 1263}; 1264 1265union cvmx_ipd_red_bpid_enablex { 1266 uint64_t u64; 1267 struct cvmx_ipd_red_bpid_enablex_s { 1268#ifdef __BIG_ENDIAN_BITFIELD 1269 uint64_t prt_enb:64; 1270#else 1271 uint64_t prt_enb:64; 1272#endif 1273 } s; 1274}; 1275 1276union cvmx_ipd_red_delay { 1277 uint64_t u64; 1278 struct cvmx_ipd_red_delay_s { 1279#ifdef __BIG_ENDIAN_BITFIELD 1280 uint64_t reserved_28_63:36; 1281 uint64_t prb_dly:14; 1282 uint64_t avg_dly:14; 1283#else 1284 uint64_t avg_dly:14; 1285 uint64_t prb_dly:14; 1286 uint64_t reserved_28_63:36; 1287#endif 1288 } s; 1289}; 1290 1291union cvmx_ipd_red_port_enable { 1292 uint64_t u64; 1293 struct cvmx_ipd_red_port_enable_s { 1294#ifdef __BIG_ENDIAN_BITFIELD 1295 uint64_t prb_dly:14; 1296 uint64_t avg_dly:14; 1297 uint64_t prt_enb:36; 1298#else 1299 uint64_t prt_enb:36; 1300 uint64_t avg_dly:14; 1301 uint64_t prb_dly:14; 1302#endif 1303 } s; 1304}; 1305 1306union cvmx_ipd_red_port_enable2 { 1307 uint64_t u64; 1308 struct cvmx_ipd_red_port_enable2_s { 1309#ifdef __BIG_ENDIAN_BITFIELD 1310 uint64_t reserved_12_63:52; 1311 uint64_t prt_enb:12; 1312#else 1313 uint64_t prt_enb:12; 1314 uint64_t reserved_12_63:52; 1315#endif 1316 } s; 1317 struct cvmx_ipd_red_port_enable2_cn52xx { 1318#ifdef __BIG_ENDIAN_BITFIELD 1319 uint64_t reserved_4_63:60; 1320 uint64_t prt_enb:4; 1321#else 1322 uint64_t prt_enb:4; 1323 uint64_t reserved_4_63:60; 1324#endif 1325 } cn52xx; 1326 struct cvmx_ipd_red_port_enable2_cn63xx { 1327#ifdef __BIG_ENDIAN_BITFIELD 1328 uint64_t reserved_8_63:56; 1329 uint64_t prt_enb:8; 1330#else 1331 uint64_t prt_enb:8; 1332 uint64_t reserved_8_63:56; 1333#endif 1334 } cn63xx; 1335}; 1336 1337union cvmx_ipd_red_quex_param { 1338 uint64_t u64; 1339 struct cvmx_ipd_red_quex_param_s { 1340#ifdef __BIG_ENDIAN_BITFIELD 1341 uint64_t reserved_49_63:15; 1342 uint64_t use_pcnt:1; 1343 uint64_t new_con:8; 1344 uint64_t avg_con:8; 1345 uint64_t prb_con:32; 1346#else 1347 uint64_t prb_con:32; 1348 uint64_t avg_con:8; 1349 uint64_t new_con:8; 1350 uint64_t use_pcnt:1; 1351 uint64_t reserved_49_63:15; 1352#endif 1353 } s; 1354}; 1355 1356union cvmx_ipd_req_wgt { 1357 uint64_t u64; 1358 struct cvmx_ipd_req_wgt_s { 1359#ifdef __BIG_ENDIAN_BITFIELD 1360 uint64_t wgt7:8; 1361 uint64_t wgt6:8; 1362 uint64_t wgt5:8; 1363 uint64_t wgt4:8; 1364 uint64_t wgt3:8; 1365 uint64_t wgt2:8; 1366 uint64_t wgt1:8; 1367 uint64_t wgt0:8; 1368#else 1369 uint64_t wgt0:8; 1370 uint64_t wgt1:8; 1371 uint64_t wgt2:8; 1372 uint64_t wgt3:8; 1373 uint64_t wgt4:8; 1374 uint64_t wgt5:8; 1375 uint64_t wgt6:8; 1376 uint64_t wgt7:8; 1377#endif 1378 } s; 1379}; 1380 1381union cvmx_ipd_sub_port_bp_page_cnt { 1382 uint64_t u64; 1383 struct cvmx_ipd_sub_port_bp_page_cnt_s { 1384#ifdef __BIG_ENDIAN_BITFIELD 1385 uint64_t reserved_31_63:33; 1386 uint64_t port:6; 1387 uint64_t page_cnt:25; 1388#else 1389 uint64_t page_cnt:25; 1390 uint64_t port:6; 1391 uint64_t reserved_31_63:33; 1392#endif 1393 } s; 1394}; 1395 1396union cvmx_ipd_sub_port_fcs { 1397 uint64_t u64; 1398 struct cvmx_ipd_sub_port_fcs_s { 1399#ifdef __BIG_ENDIAN_BITFIELD 1400 uint64_t reserved_40_63:24; 1401 uint64_t port_bit2:4; 1402 uint64_t reserved_32_35:4; 1403 uint64_t port_bit:32; 1404#else 1405 uint64_t port_bit:32; 1406 uint64_t reserved_32_35:4; 1407 uint64_t port_bit2:4; 1408 uint64_t reserved_40_63:24; 1409#endif 1410 } s; 1411 struct cvmx_ipd_sub_port_fcs_cn30xx { 1412#ifdef __BIG_ENDIAN_BITFIELD 1413 uint64_t reserved_3_63:61; 1414 uint64_t port_bit:3; 1415#else 1416 uint64_t port_bit:3; 1417 uint64_t reserved_3_63:61; 1418#endif 1419 } cn30xx; 1420 struct cvmx_ipd_sub_port_fcs_cn38xx { 1421#ifdef __BIG_ENDIAN_BITFIELD 1422 uint64_t reserved_32_63:32; 1423 uint64_t port_bit:32; 1424#else 1425 uint64_t port_bit:32; 1426 uint64_t reserved_32_63:32; 1427#endif 1428 } cn38xx; 1429}; 1430 1431union cvmx_ipd_sub_port_qos_cnt { 1432 uint64_t u64; 1433 struct cvmx_ipd_sub_port_qos_cnt_s { 1434#ifdef __BIG_ENDIAN_BITFIELD 1435 uint64_t reserved_41_63:23; 1436 uint64_t port_qos:9; 1437 uint64_t cnt:32; 1438#else 1439 uint64_t cnt:32; 1440 uint64_t port_qos:9; 1441 uint64_t reserved_41_63:23; 1442#endif 1443 } s; 1444}; 1445 1446union cvmx_ipd_wqe_fpa_queue { 1447 uint64_t u64; 1448 struct cvmx_ipd_wqe_fpa_queue_s { 1449#ifdef __BIG_ENDIAN_BITFIELD 1450 uint64_t reserved_3_63:61; 1451 uint64_t wqe_pool:3; 1452#else 1453 uint64_t wqe_pool:3; 1454 uint64_t reserved_3_63:61; 1455#endif 1456 } s; 1457}; 1458 1459union cvmx_ipd_wqe_ptr_valid { 1460 uint64_t u64; 1461 struct cvmx_ipd_wqe_ptr_valid_s { 1462#ifdef __BIG_ENDIAN_BITFIELD 1463 uint64_t reserved_29_63:35; 1464 uint64_t ptr:29; 1465#else 1466 uint64_t ptr:29; 1467 uint64_t reserved_29_63:35; 1468#endif 1469 } s; 1470}; 1471 1472#endif 1473