1/*
2 * Copyright (c) 2003-2016 Cavium Inc.
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 *
8 * This file is distributed in the hope that it will be useful, but
9 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
11 * NONINFRINGEMENT.  See the GNU General Public License for more
12 * details.
13 *
14 */
15
16#ifndef __CVMX_CIU3_DEFS_H__
17#define __CVMX_CIU3_DEFS_H__
18
19#define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull)
20#define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull)
21#define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull)
22#define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull)
23#define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8)
24#define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8)
25#define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull)
26#define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8)
27#define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8)
28#define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull)
29#define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull)
30#define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull)
31#define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull)
32#define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull)
33#define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8)
34#define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8)
35#define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8)
36#define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull)
37#define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8)
38#define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8)
39
40union cvmx_ciu3_bist {
41	uint64_t u64;
42	struct cvmx_ciu3_bist_s {
43#ifdef __BIG_ENDIAN_BITFIELD
44	uint64_t reserved_9_63                : 55;
45	uint64_t bist                         : 9;
46#else
47	uint64_t bist                         : 9;
48	uint64_t reserved_9_63                : 55;
49#endif
50	} s;
51};
52
53union cvmx_ciu3_const {
54	uint64_t u64;
55	struct cvmx_ciu3_const_s {
56#ifdef __BIG_ENDIAN_BITFIELD
57	uint64_t dests_io                     : 16;
58	uint64_t pintsn                       : 16;
59	uint64_t dests_pp                     : 16;
60	uint64_t idt                          : 16;
61#else
62	uint64_t idt                          : 16;
63	uint64_t dests_pp                     : 16;
64	uint64_t pintsn                       : 16;
65	uint64_t dests_io                     : 16;
66#endif
67	} s;
68};
69
70union cvmx_ciu3_ctl {
71	uint64_t u64;
72	struct cvmx_ciu3_ctl_s {
73#ifdef __BIG_ENDIAN_BITFIELD
74	uint64_t reserved_5_63                : 59;
75	uint64_t mcd_sel                      : 2;
76	uint64_t iscmem_le                    : 1;
77	uint64_t seq_dis                      : 1;
78	uint64_t cclk_dis                     : 1;
79#else
80	uint64_t cclk_dis                     : 1;
81	uint64_t seq_dis                      : 1;
82	uint64_t iscmem_le                    : 1;
83	uint64_t mcd_sel                      : 2;
84	uint64_t reserved_5_63                : 59;
85#endif
86	} s;
87};
88
89union cvmx_ciu3_destx_io_int {
90	uint64_t u64;
91	struct cvmx_ciu3_destx_io_int_s {
92#ifdef __BIG_ENDIAN_BITFIELD
93	uint64_t reserved_52_63               : 12;
94	uint64_t intsn                        : 20;
95	uint64_t reserved_10_31               : 22;
96	uint64_t intidt                       : 8;
97	uint64_t newint                       : 1;
98	uint64_t intr                         : 1;
99#else
100	uint64_t intr                         : 1;
101	uint64_t newint                       : 1;
102	uint64_t intidt                       : 8;
103	uint64_t reserved_10_31               : 22;
104	uint64_t intsn                        : 20;
105	uint64_t reserved_52_63               : 12;
106#endif
107	} s;
108};
109
110union cvmx_ciu3_destx_pp_int {
111	uint64_t u64;
112	struct cvmx_ciu3_destx_pp_int_s {
113#ifdef __BIG_ENDIAN_BITFIELD
114	uint64_t reserved_52_63               : 12;
115	uint64_t intsn                        : 20;
116	uint64_t reserved_10_31               : 22;
117	uint64_t intidt                       : 8;
118	uint64_t newint                       : 1;
119	uint64_t intr                         : 1;
120#else
121	uint64_t intr                         : 1;
122	uint64_t newint                       : 1;
123	uint64_t intidt                       : 8;
124	uint64_t reserved_10_31               : 22;
125	uint64_t intsn                        : 20;
126	uint64_t reserved_52_63               : 12;
127#endif
128	} s;
129};
130
131union cvmx_ciu3_gstop {
132	uint64_t u64;
133	struct cvmx_ciu3_gstop_s {
134#ifdef __BIG_ENDIAN_BITFIELD
135	uint64_t reserved_1_63                : 63;
136	uint64_t gstop                        : 1;
137#else
138	uint64_t gstop                        : 1;
139	uint64_t reserved_1_63                : 63;
140#endif
141	} s;
142};
143
144union cvmx_ciu3_idtx_ctl {
145	uint64_t u64;
146	struct cvmx_ciu3_idtx_ctl_s {
147#ifdef __BIG_ENDIAN_BITFIELD
148	uint64_t reserved_52_63               : 12;
149	uint64_t intsn                        : 20;
150	uint64_t reserved_4_31                : 28;
151	uint64_t intr                         : 1;
152	uint64_t newint                       : 1;
153	uint64_t ip_num                       : 2;
154#else
155	uint64_t ip_num                       : 2;
156	uint64_t newint                       : 1;
157	uint64_t intr                         : 1;
158	uint64_t reserved_4_31                : 28;
159	uint64_t intsn                        : 20;
160	uint64_t reserved_52_63               : 12;
161#endif
162	} s;
163};
164
165union cvmx_ciu3_idtx_io {
166	uint64_t u64;
167	struct cvmx_ciu3_idtx_io_s {
168#ifdef __BIG_ENDIAN_BITFIELD
169	uint64_t reserved_5_63                : 59;
170	uint64_t io                           : 5;
171#else
172	uint64_t io                           : 5;
173	uint64_t reserved_5_63                : 59;
174#endif
175	} s;
176};
177
178union cvmx_ciu3_idtx_ppx {
179	uint64_t u64;
180	struct cvmx_ciu3_idtx_ppx_s {
181#ifdef __BIG_ENDIAN_BITFIELD
182	uint64_t reserved_48_63               : 16;
183	uint64_t pp                           : 48;
184#else
185	uint64_t pp                           : 48;
186	uint64_t reserved_48_63               : 16;
187#endif
188	} s;
189};
190
191union cvmx_ciu3_intr_ram_ecc_ctl {
192	uint64_t u64;
193	struct cvmx_ciu3_intr_ram_ecc_ctl_s {
194#ifdef __BIG_ENDIAN_BITFIELD
195	uint64_t reserved_3_63                : 61;
196	uint64_t flip_synd                    : 2;
197	uint64_t ecc_ena                      : 1;
198#else
199	uint64_t ecc_ena                      : 1;
200	uint64_t flip_synd                    : 2;
201	uint64_t reserved_3_63                : 61;
202#endif
203	} s;
204};
205
206union cvmx_ciu3_intr_ram_ecc_st {
207	uint64_t u64;
208	struct cvmx_ciu3_intr_ram_ecc_st_s {
209#ifdef __BIG_ENDIAN_BITFIELD
210	uint64_t reserved_52_63               : 12;
211	uint64_t addr                         : 20;
212	uint64_t reserved_6_31                : 26;
213	uint64_t sisc_dbe                     : 1;
214	uint64_t sisc_sbe                     : 1;
215	uint64_t idt_dbe                      : 1;
216	uint64_t idt_sbe                      : 1;
217	uint64_t isc_dbe                      : 1;
218	uint64_t isc_sbe                      : 1;
219#else
220	uint64_t isc_sbe                      : 1;
221	uint64_t isc_dbe                      : 1;
222	uint64_t idt_sbe                      : 1;
223	uint64_t idt_dbe                      : 1;
224	uint64_t sisc_sbe                     : 1;
225	uint64_t sisc_dbe                     : 1;
226	uint64_t reserved_6_31                : 26;
227	uint64_t addr                         : 20;
228	uint64_t reserved_52_63               : 12;
229#endif
230	} s;
231};
232
233union cvmx_ciu3_intr_ready {
234	uint64_t u64;
235	struct cvmx_ciu3_intr_ready_s {
236#ifdef __BIG_ENDIAN_BITFIELD
237	uint64_t reserved_46_63               : 18;
238	uint64_t index                        : 14;
239	uint64_t reserved_1_31                : 31;
240	uint64_t ready                        : 1;
241#else
242	uint64_t ready                        : 1;
243	uint64_t reserved_1_31                : 31;
244	uint64_t index                        : 14;
245	uint64_t reserved_46_63               : 18;
246#endif
247	} s;
248};
249
250union cvmx_ciu3_intr_slowdown {
251	uint64_t u64;
252	struct cvmx_ciu3_intr_slowdown_s {
253#ifdef __BIG_ENDIAN_BITFIELD
254	uint64_t reserved_3_63                : 61;
255	uint64_t ctl                          : 3;
256#else
257	uint64_t ctl                          : 3;
258	uint64_t reserved_3_63                : 61;
259#endif
260	} s;
261};
262
263union cvmx_ciu3_iscx_ctl {
264	uint64_t u64;
265	struct cvmx_ciu3_iscx_ctl_s {
266#ifdef __BIG_ENDIAN_BITFIELD
267	uint64_t reserved_24_63               : 40;
268	uint64_t idt                          : 8;
269	uint64_t imp                          : 1;
270	uint64_t reserved_2_14                : 13;
271	uint64_t en                           : 1;
272	uint64_t raw                          : 1;
273#else
274	uint64_t raw                          : 1;
275	uint64_t en                           : 1;
276	uint64_t reserved_2_14                : 13;
277	uint64_t imp                          : 1;
278	uint64_t idt                          : 8;
279	uint64_t reserved_24_63               : 40;
280#endif
281	} s;
282};
283
284union cvmx_ciu3_iscx_w1c {
285	uint64_t u64;
286	struct cvmx_ciu3_iscx_w1c_s {
287#ifdef __BIG_ENDIAN_BITFIELD
288	uint64_t reserved_2_63                : 62;
289	uint64_t en                           : 1;
290	uint64_t raw                          : 1;
291#else
292	uint64_t raw                          : 1;
293	uint64_t en                           : 1;
294	uint64_t reserved_2_63                : 62;
295#endif
296	} s;
297};
298
299union cvmx_ciu3_iscx_w1s {
300	uint64_t u64;
301	struct cvmx_ciu3_iscx_w1s_s {
302#ifdef __BIG_ENDIAN_BITFIELD
303	uint64_t reserved_2_63                : 62;
304	uint64_t en                           : 1;
305	uint64_t raw                          : 1;
306#else
307	uint64_t raw                          : 1;
308	uint64_t en                           : 1;
309	uint64_t reserved_2_63                : 62;
310#endif
311	} s;
312};
313
314union cvmx_ciu3_nmi {
315	uint64_t u64;
316	struct cvmx_ciu3_nmi_s {
317#ifdef __BIG_ENDIAN_BITFIELD
318	uint64_t reserved_48_63               : 16;
319	uint64_t nmi                          : 48;
320#else
321	uint64_t nmi                          : 48;
322	uint64_t reserved_48_63               : 16;
323#endif
324	} s;
325};
326
327union cvmx_ciu3_siscx {
328	uint64_t u64;
329	struct cvmx_ciu3_siscx_s {
330#ifdef __BIG_ENDIAN_BITFIELD
331	uint64_t en                           : 64;
332#else
333	uint64_t en                           : 64;
334#endif
335	} s;
336};
337
338union cvmx_ciu3_timx {
339	uint64_t u64;
340	struct cvmx_ciu3_timx_s {
341#ifdef __BIG_ENDIAN_BITFIELD
342	uint64_t reserved_37_63               : 27;
343	uint64_t one_shot                     : 1;
344	uint64_t len                          : 36;
345#else
346	uint64_t len                          : 36;
347	uint64_t one_shot                     : 1;
348	uint64_t reserved_37_63               : 27;
349#endif
350	} s;
351};
352
353#endif
354