1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
5 *
6 * Defines of the Malta board specific address-MAP, registers, etc.
7 */
8#ifndef __ASM_MIPS_BOARDS_MALTA_H
9#define __ASM_MIPS_BOARDS_MALTA_H
10
11#include <asm/addrspace.h>
12#include <asm/io.h>
13#include <asm/mips-boards/msc01_pci.h>
14#include <asm/gt64120.h>
15
16/* Mips interrupt controller found in SOCit variations */
17#define MIPS_MSC01_IC_REG_BASE		0x1bc40000
18#define MIPS_SOCITSC_IC_REG_BASE	0x1ffa0000
19
20/*
21 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
22 * Bonito system controllers.
23 */
24#define MALTA_GT_PORT_BASE	get_gt_port_base(GT_PCI0IOLD_OFS)
25#define MALTA_BONITO_PORT_BASE	((unsigned long)ioremap (0x1fd00000, 0x10000))
26#define MALTA_MSC_PORT_BASE	get_msc_port_base(MSC01_PCI_SC2PIOBASL)
27
28static inline unsigned long get_gt_port_base(unsigned long reg)
29{
30	unsigned long addr;
31	addr = GT_READ(reg);
32	return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
33}
34
35static inline unsigned long get_msc_port_base(unsigned long reg)
36{
37	unsigned long addr;
38	MSC_READ(reg, addr);
39	return (unsigned long) ioremap(addr, 0x10000);
40}
41
42/*
43 * GCMP Specific definitions
44 */
45#define GCMP_BASE_ADDR			0x1fbf8000
46#define GCMP_ADDRSPACE_SZ		(256 * 1024)
47
48/*
49 * GIC Specific definitions
50 */
51#define GIC_BASE_ADDR			0x1bdc0000
52#define GIC_ADDRSPACE_SZ		(128 * 1024)
53
54/*
55 * CPC Specific definitions
56 */
57#define CPC_BASE_ADDR			0x1bde0000
58
59/*
60 * MSC01 BIU Specific definitions
61 * FIXME : These should be elsewhere ?
62 */
63#define MSC01_BIU_REG_BASE		0x1bc80000
64#define MSC01_BIU_ADDRSPACE_SZ		(256 * 1024)
65#define MSC01_SC_CFG_OFS		0x0110
66#define MSC01_SC_CFG_GICPRES_MSK	0x00000004
67#define MSC01_SC_CFG_GICPRES_SHF	2
68#define MSC01_SC_CFG_GICENA_SHF		3
69
70/*
71 * Malta RTC-device indirect register access.
72 */
73#define MALTA_RTC_ADR_REG	0x70
74#define MALTA_RTC_DAT_REG	0x71
75
76/*
77 * Malta SMSC FDC37M817 Super I/O Controller register.
78 */
79#define SMSC_CONFIG_REG		0x3f0
80#define SMSC_DATA_REG		0x3f1
81
82#define SMSC_CONFIG_DEVNUM	0x7
83#define SMSC_CONFIG_ACTIVATE	0x30
84#define SMSC_CONFIG_ENTER	0x55
85#define SMSC_CONFIG_EXIT	0xaa
86
87#define SMSC_CONFIG_DEVNUM_FLOPPY     0
88
89#define SMSC_CONFIG_ACTIVATE_ENABLE   1
90
91#define SMSC_WRITE(x, a)     outb(x, a)
92
93#define MALTA_JMPRS_REG		0x1f000210
94
95extern void __init *malta_dt_shim(void *fdt);
96
97#endif /* __ASM_MIPS_BOARDS_MALTA_H */
98