1/*
2 * Read/Write Loongson Extension Registers
3 */
4
5#ifndef _LOONGSON_REGS_H_
6#define _LOONGSON_REGS_H_
7
8#include <linux/types.h>
9#include <linux/bits.h>
10
11#include <asm/mipsregs.h>
12#include <asm/cpu.h>
13
14static inline bool cpu_has_cfg(void)
15{
16	return ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G);
17}
18
19static inline u32 read_cpucfg(u32 reg)
20{
21	u32 __res;
22
23	__asm__ __volatile__(
24		_ASM_SET_PARSE_R
25		"parse_r __res,%0\n\t"
26		"parse_r reg,%1\n\t"
27		_ASM_UNSET_PARSE_R
28		".insn \n\t"
29		".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
30		:"=r"(__res)
31		:"r"(reg)
32		:
33		);
34	return __res;
35}
36
37/* Bit Domains for CFG registers */
38#define LOONGSON_CFG0	0x0
39#define LOONGSON_CFG0_PRID GENMASK(31, 0)
40
41#define LOONGSON_CFG1 0x1
42#define LOONGSON_CFG1_FP	BIT(0)
43#define LOONGSON_CFG1_FPREV	GENMASK(3, 1)
44#define LOONGSON_CFG1_MMI	BIT(4)
45#define LOONGSON_CFG1_MSA1	BIT(5)
46#define LOONGSON_CFG1_MSA2	BIT(6)
47#define LOONGSON_CFG1_CGP	BIT(7)
48#define LOONGSON_CFG1_WRP	BIT(8)
49#define LOONGSON_CFG1_LSX1	BIT(9)
50#define LOONGSON_CFG1_LSX2	BIT(10)
51#define LOONGSON_CFG1_LASX	BIT(11)
52#define LOONGSON_CFG1_R6FXP	BIT(12)
53#define LOONGSON_CFG1_R6CRCP	BIT(13)
54#define LOONGSON_CFG1_R6FPP	BIT(14)
55#define LOONGSON_CFG1_CNT64	BIT(15)
56#define LOONGSON_CFG1_LSLDR0	BIT(16)
57#define LOONGSON_CFG1_LSPREF	BIT(17)
58#define LOONGSON_CFG1_LSPREFX	BIT(18)
59#define LOONGSON_CFG1_LSSYNCI	BIT(19)
60#define LOONGSON_CFG1_LSUCA	BIT(20)
61#define LOONGSON_CFG1_LLSYNC	BIT(21)
62#define LOONGSON_CFG1_TGTSYNC	BIT(22)
63#define LOONGSON_CFG1_LLEXC	BIT(23)
64#define LOONGSON_CFG1_SCRAND	BIT(24)
65#define LOONGSON_CFG1_MUALP	BIT(25)
66#define LOONGSON_CFG1_KMUALEN	BIT(26)
67#define LOONGSON_CFG1_ITLBT	BIT(27)
68#define LOONGSON_CFG1_LSUPERF	BIT(28)
69#define LOONGSON_CFG1_SFBP	BIT(29)
70#define LOONGSON_CFG1_CDMAP	BIT(30)
71
72#define LOONGSON_CFG1_FPREV_OFFSET	1
73
74#define LOONGSON_CFG2 0x2
75#define LOONGSON_CFG2_LEXT1	BIT(0)
76#define LOONGSON_CFG2_LEXT2	BIT(1)
77#define LOONGSON_CFG2_LEXT3	BIT(2)
78#define LOONGSON_CFG2_LSPW	BIT(3)
79#define LOONGSON_CFG2_LBT1	BIT(4)
80#define LOONGSON_CFG2_LBT2	BIT(5)
81#define LOONGSON_CFG2_LBT3	BIT(6)
82#define LOONGSON_CFG2_LBTMMU	BIT(7)
83#define LOONGSON_CFG2_LPMP	BIT(8)
84#define LOONGSON_CFG2_LPMREV	GENMASK(11, 9)
85#define LOONGSON_CFG2_LAMO	BIT(12)
86#define LOONGSON_CFG2_LPIXU	BIT(13)
87#define LOONGSON_CFG2_LPIXNU	BIT(14)
88#define LOONGSON_CFG2_LVZP	BIT(15)
89#define LOONGSON_CFG2_LVZREV	GENMASK(18, 16)
90#define LOONGSON_CFG2_LGFTP	BIT(19)
91#define LOONGSON_CFG2_LGFTPREV	GENMASK(22, 20)
92#define LOONGSON_CFG2_LLFTP	BIT(23)
93#define LOONGSON_CFG2_LLFTPREV	GENMASK(26, 24)
94#define LOONGSON_CFG2_LCSRP	BIT(27)
95#define LOONGSON_CFG2_LDISBLIKELY	BIT(28)
96
97#define LOONGSON_CFG2_LPMREV_OFFSET	9
98#define LOONGSON_CFG2_LPM_REV1		(1 << LOONGSON_CFG2_LPMREV_OFFSET)
99#define LOONGSON_CFG2_LPM_REV2		(2 << LOONGSON_CFG2_LPMREV_OFFSET)
100#define LOONGSON_CFG2_LVZREV_OFFSET	16
101#define LOONGSON_CFG2_LVZ_REV1		(1 << LOONGSON_CFG2_LVZREV_OFFSET)
102#define LOONGSON_CFG2_LVZ_REV2		(2 << LOONGSON_CFG2_LVZREV_OFFSET)
103
104#define LOONGSON_CFG3 0x3
105#define LOONGSON_CFG3_LCAMP	BIT(0)
106#define LOONGSON_CFG3_LCAMREV	GENMASK(3, 1)
107#define LOONGSON_CFG3_LCAMNUM	GENMASK(11, 4)
108#define LOONGSON_CFG3_LCAMKW	GENMASK(19, 12)
109#define LOONGSON_CFG3_LCAMVW	GENMASK(27, 20)
110
111#define LOONGSON_CFG3_LCAMREV_OFFSET	1
112#define LOONGSON_CFG3_LCAM_REV1		(1 << LOONGSON_CFG3_LCAMREV_OFFSET)
113#define LOONGSON_CFG3_LCAM_REV2		(2 << LOONGSON_CFG3_LCAMREV_OFFSET)
114#define LOONGSON_CFG3_LCAMNUM_OFFSET	4
115#define LOONGSON_CFG3_LCAMNUM_REV1	(0x3f << LOONGSON_CFG3_LCAMNUM_OFFSET)
116#define LOONGSON_CFG3_LCAMKW_OFFSET	12
117#define LOONGSON_CFG3_LCAMKW_REV1	(0x27 << LOONGSON_CFG3_LCAMKW_OFFSET)
118#define LOONGSON_CFG3_LCAMVW_OFFSET	20
119#define LOONGSON_CFG3_LCAMVW_REV1	(0x3f << LOONGSON_CFG3_LCAMVW_OFFSET)
120
121#define LOONGSON_CFG4 0x4
122#define LOONGSON_CFG4_CCFREQ	GENMASK(31, 0)
123
124#define LOONGSON_CFG5 0x5
125#define LOONGSON_CFG5_CFM	GENMASK(15, 0)
126#define LOONGSON_CFG5_CFD	GENMASK(31, 16)
127
128#define LOONGSON_CFG6 0x6
129
130#define LOONGSON_CFG7 0x7
131#define LOONGSON_CFG7_GCCAEQRP	BIT(0)
132#define LOONGSON_CFG7_UCAWINP	BIT(1)
133
134static inline bool cpu_has_csr(void)
135{
136	if (cpu_has_cfg())
137		return (read_cpucfg(LOONGSON_CFG2) & LOONGSON_CFG2_LCSRP);
138
139	return false;
140}
141
142static inline u32 csr_readl(u32 reg)
143{
144	u32 __res;
145
146	/* RDCSR reg, val */
147	__asm__ __volatile__(
148		_ASM_SET_PARSE_R
149		"parse_r __res,%0\n\t"
150		"parse_r reg,%1\n\t"
151		_ASM_UNSET_PARSE_R
152		".insn \n\t"
153		".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t"
154		:"=r"(__res)
155		:"r"(reg)
156		:
157		);
158	return __res;
159}
160
161static inline u64 csr_readq(u32 reg)
162{
163	u64 __res;
164
165	/* DRDCSR reg, val */
166	__asm__ __volatile__(
167		_ASM_SET_PARSE_R
168		"parse_r __res,%0\n\t"
169		"parse_r reg,%1\n\t"
170		_ASM_UNSET_PARSE_R
171		".insn \n\t"
172		".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t"
173		:"=r"(__res)
174		:"r"(reg)
175		:
176		);
177	return __res;
178}
179
180static inline void csr_writel(u32 val, u32 reg)
181{
182	/* WRCSR reg, val */
183	__asm__ __volatile__(
184		_ASM_SET_PARSE_R
185		"parse_r reg,%0\n\t"
186		"parse_r val,%1\n\t"
187		_ASM_UNSET_PARSE_R
188		".insn \n\t"
189		".word (0xc8010118 | (reg << 21) | (val << 11))\n\t"
190		:
191		:"r"(reg),"r"(val)
192		:
193		);
194}
195
196static inline void csr_writeq(u64 val, u32 reg)
197{
198	/* DWRCSR reg, val */
199	__asm__ __volatile__(
200		_ASM_SET_PARSE_R
201		"parse_r reg,%0\n\t"
202		"parse_r val,%1\n\t"
203		_ASM_UNSET_PARSE_R
204		".insn \n\t"
205		".word (0xc8030118 | (reg << 21) | (val << 11))\n\t"
206		:
207		:"r"(reg),"r"(val)
208		:
209		);
210}
211
212/* Public CSR Register can also be accessed with regular addresses */
213#define CSR_PUBLIC_MMIO_BASE 0x1fe00000
214
215#define MMIO_CSR(x)		(void *)TO_UNCAC(CSR_PUBLIC_MMIO_BASE + x)
216
217#define LOONGSON_CSR_FEATURES	0x8
218#define LOONGSON_CSRF_TEMP	BIT(0)
219#define LOONGSON_CSRF_NODECNT	BIT(1)
220#define LOONGSON_CSRF_MSI	BIT(2)
221#define LOONGSON_CSRF_EXTIOI	BIT(3)
222#define LOONGSON_CSRF_IPI	BIT(4)
223#define LOONGSON_CSRF_FREQ	BIT(5)
224
225#define LOONGSON_CSR_VENDOR	0x10 /* Vendor name string, should be "Loongson" */
226#define LOONGSON_CSR_CPUNAME	0x20 /* Processor name string */
227#define LOONGSON_CSR_NODECNT	0x408
228#define LOONGSON_CSR_CPUTEMP	0x428
229
230/* PerCore CSR, only accessible by local cores */
231#define LOONGSON_CSR_IPI_STATUS	0x1000
232#define LOONGSON_CSR_IPI_EN	0x1004
233#define LOONGSON_CSR_IPI_SET	0x1008
234#define LOONGSON_CSR_IPI_CLEAR	0x100c
235#define LOONGSON_CSR_IPI_SEND	0x1040
236#define CSR_IPI_SEND_IP_SHIFT	0
237#define CSR_IPI_SEND_CPU_SHIFT	16
238#define CSR_IPI_SEND_BLOCK	BIT(31)
239
240#define LOONGSON_CSR_MAIL_BUF0		0x1020
241#define LOONGSON_CSR_MAIL_SEND		0x1048
242#define CSR_MAIL_SEND_BLOCK		BIT_ULL(31)
243#define CSR_MAIL_SEND_BOX_LOW(box)	(box << 1)
244#define CSR_MAIL_SEND_BOX_HIGH(box)	((box << 1) + 1)
245#define CSR_MAIL_SEND_BOX_SHIFT		2
246#define CSR_MAIL_SEND_CPU_SHIFT		16
247#define CSR_MAIL_SEND_BUF_SHIFT		32
248#define CSR_MAIL_SEND_H32_MASK		0xFFFFFFFF00000000ULL
249
250static inline u64 drdtime(void)
251{
252	int rID = 0;
253	u64 val = 0;
254
255	__asm__ __volatile__(
256		_ASM_SET_PARSE_R
257		"parse_r rID,%0\n\t"
258		"parse_r val,%1\n\t"
259		_ASM_UNSET_PARSE_R
260		".insn \n\t"
261		".word (0xc8090118 | (rID << 21) | (val << 11))\n\t"
262		:"=r"(rID),"=r"(val)
263		:
264		);
265	return val;
266}
267
268#endif
269