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2f9060b1 |
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03-Jan-2024 |
Bjorn Helgaas <bhelgaas@google.com> |
MIPS: Fix typos Fix typos, most reported by "codespell arch/mips". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-mips@vger.kernel.org Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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67512a8c |
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13-Sep-2021 |
Paul Cercueil <paul@crapouillou.net> |
MIPS: Avoid macro redefinitions To be able to compile the kernel with LTO, the assembler macros cannot be declared in the global scope, or the compiler will complain about redefined macros. Update the code so that macros are defined then undefined when they are used. Note that virt support was added in 2.24 and xpa in 2.25. So we still need the TOOLCHAIN defines for them. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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fed4955f |
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03-Nov-2020 |
Tiezhu Yang <yangtiezhu@loongson.cn> |
MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Loongson 3A4000+ CPU has per-core Mail_Send register to send mail, there is no need to maintain register address of each core and node, just simply specify cpu number. Signed-off-by: Lu Zeng <zenglu@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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fdec207e |
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03-May-2020 |
WANG Xuerui <git@xen0n.name> |
MIPS: Loongson64: define offsets and known revisions for some CPUCFG features Add the constants for easier and maintainable composition of CPUCFG values. Signed-off-by: WANG Xuerui <git@xen0n.name> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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de541d60 |
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03-May-2020 |
WANG Xuerui <git@xen0n.name> |
MIPS: Loongson64: fix typos in loongson_regs.h Fix some symbol names to align with Loongson's User Manual wording. Also correct the comment in csr_readq() suggesting the wrong instruction in use. Fixes: 6a6f9b7dafd50efc ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: WANG Xuerui <git@xen0n.name> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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e02d026f |
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22-Oct-2019 |
Rikard Falkeborn <rikard.falkeborn@gmail.com> |
MIPS: Loongson: Fix GENMASK misuse Arguments are supposed to be ordered high then low. Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: chenhuacai@gmail.com Cc: jhogan@kernel.org Cc: jiaxun.yang@flygoat.com Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: paul.burton@mips.com Cc: ralf@linux-mips.org Cc: wuzhangjin@gmail.com Cc: zhangfx@lemote.com
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6a6f9b7d |
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21-Sep-2019 |
Huacai Chen <chenhuacai@kernel.org> |
MIPS: Loongson: Add CFUCFG&CSR support Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and CSR (Control and Status Register) extensions. This patch add read/write functionalities for them. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
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