1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 *  Copyright (C) 2010 John Crispin <john@phrozen.org>
5 */
6
7#ifndef _LTQ_XWAY_H__
8#define _LTQ_XWAY_H__
9
10#ifdef CONFIG_SOC_TYPE_XWAY
11
12#include <lantiq.h>
13
14/* Chip IDs */
15#define SOC_ID_DANUBE1		0x129
16#define SOC_ID_DANUBE2		0x12B
17#define SOC_ID_TWINPASS		0x12D
18#define SOC_ID_AMAZON_SE_1	0x152 /* 50601 */
19#define SOC_ID_AMAZON_SE_2	0x153 /* 50600 */
20#define SOC_ID_ARX188		0x16C
21#define SOC_ID_ARX168_1		0x16D
22#define SOC_ID_ARX168_2		0x16E
23#define SOC_ID_ARX182		0x16F
24#define SOC_ID_GRX188		0x170
25#define SOC_ID_GRX168		0x171
26
27#define SOC_ID_VRX288		0x1C0 /* v1.1 */
28#define SOC_ID_VRX282		0x1C1 /* v1.1 */
29#define SOC_ID_VRX268		0x1C2 /* v1.1 */
30#define SOC_ID_GRX268		0x1C8 /* v1.1 */
31#define SOC_ID_GRX288		0x1C9 /* v1.1 */
32#define SOC_ID_VRX288_2		0x00B /* v1.2 */
33#define SOC_ID_VRX268_2		0x00C /* v1.2 */
34#define SOC_ID_GRX288_2		0x00D /* v1.2 */
35#define SOC_ID_GRX282_2		0x00E /* v1.2 */
36#define SOC_ID_VRX220		0x000
37
38#define SOC_ID_ARX362		0x004
39#define SOC_ID_ARX368		0x005
40#define SOC_ID_ARX382		0x007
41#define SOC_ID_ARX388		0x008
42#define SOC_ID_URX388		0x009
43#define SOC_ID_GRX383		0x010
44#define SOC_ID_GRX369		0x011
45#define SOC_ID_GRX387		0x00F
46#define SOC_ID_GRX389		0x012
47
48 /* SoC Types */
49#define SOC_TYPE_DANUBE		0x01
50#define SOC_TYPE_TWINPASS	0x02
51#define SOC_TYPE_AR9		0x03
52#define SOC_TYPE_VR9		0x04 /* v1.1 */
53#define SOC_TYPE_VR9_2		0x05 /* v1.2 */
54#define SOC_TYPE_AMAZON_SE	0x06
55#define SOC_TYPE_AR10		0x07
56#define SOC_TYPE_GRX390		0x08
57#define SOC_TYPE_VRX220		0x09
58
59/* BOOT_SEL - find what boot media we have */
60#define BS_EXT_ROM		0x0
61#define BS_FLASH		0x1
62#define BS_MII0			0x2
63#define BS_PCI			0x3
64#define BS_UART1		0x4
65#define BS_SPI			0x5
66#define BS_NAND			0x6
67#define BS_RMII0		0x7
68
69/* helpers used to access the cgu */
70#define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
71#define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
72extern __iomem void *ltq_cgu_membase;
73
74/*
75 * during early_printk no ioremap is possible
76 * let's use KSEG1 instead
77 */
78#define LTQ_ASC1_BASE_ADDR	0x1E100C00
79#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
80
81/* EBU - external bus unit */
82#define LTQ_EBU_BUSCON0		0x0060
83#define LTQ_EBU_PCC_CON		0x0090
84#define LTQ_EBU_PCC_IEN		0x00A4
85#define LTQ_EBU_PCC_ISTAT	0x00A0
86#define LTQ_EBU_BUSCON1		0x0064
87#define LTQ_EBU_ADDRSEL1	0x0024
88#define EBU_WRDIS		0x80000000
89
90/* WDT */
91#define LTQ_RST_CAUSE_WDTRST	0x20
92
93/* MPS - multi processor unit (voice) */
94#define LTQ_MPS_BASE_ADDR	(KSEG1 + 0x1F107000)
95#define LTQ_MPS_CHIPID		((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
96
97/* request a non-gpio and set the PIO config */
98#define PMU_PPE			 BIT(13)
99extern void ltq_pmu_enable(unsigned int module);
100extern void ltq_pmu_disable(unsigned int module);
101
102#endif /* CONFIG_SOC_TYPE_XWAY */
103#endif /* _LTQ_XWAY_H__ */
104