1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2010 John Crispin <john@phrozen.org>
5 */
6
7#ifndef _LTQ_FALCON_H__
8#define _LTQ_FALCON_H__
9
10#ifdef CONFIG_SOC_FALCON
11
12#include <linux/pinctrl/pinctrl.h>
13#include <lantiq.h>
14
15/* Chip IDs */
16#define SOC_ID_FALCON		0x01B8
17
18/* SoC Types */
19#define SOC_TYPE_FALCON		0x01
20
21/*
22 * during early_printk no ioremap possible at this early stage
23 * let's use KSEG1 instead
24 */
25#define LTQ_ASC0_BASE_ADDR	0x1E100C00
26#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
27
28/* WDT */
29#define LTQ_RST_CAUSE_WDTRST	0x0002
30
31/* CHIP ID */
32#define LTQ_STATUS_BASE_ADDR	0x1E802000
33
34#define FALCON_CHIPID		((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
35#define FALCON_CHIPTYPE		((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
36#define FALCON_CHIPCONF		((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
37
38/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
39#define SYSCTL_SYS1		0
40#define SYSCTL_SYSETH		1
41#define SYSCTL_SYSGPE		2
42
43/* BOOT_SEL - find what boot media we have */
44#define BS_FLASH		0x1
45#define BS_SPI			0x4
46
47/* global register ranges */
48extern __iomem void *ltq_ebu_membase;
49extern __iomem void *ltq_sys1_membase;
50#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
51#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
52
53#define ltq_sys1_w32(x, y)	ltq_w32((x), ltq_sys1_membase + (y))
54#define ltq_sys1_r32(x)		ltq_r32(ltq_sys1_membase + (x))
55#define ltq_sys1_w32_mask(clear, set, reg)   \
56	ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
57
58/* allow the gpio and pinctrl drivers to talk to each other */
59extern int pinctrl_falcon_get_range_size(int id);
60extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
61
62/*
63 * to keep the irq code generic we need to define this to 0 as falcon
64 * has no EIU/EBU
65 */
66#define LTQ_EBU_PCC_ISTAT	0
67
68#endif /* CONFIG_SOC_FALCON */
69#endif /* _LTQ_XWAY_H__ */
70