1/* 2 * Hardware info about DECstation 5000/2x0 systems (otherwise known as 3 * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which 4 * differ mechanically but are otherwise identical (both are known as 5 * KN03). 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 12 * are by courtesy of Chris Fraser. 13 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki 14 */ 15#ifndef __ASM_MIPS_DEC_KN03_H 16#define __ASM_MIPS_DEC_KN03_H 17 18#include <asm/dec/ecc.h> 19#include <asm/dec/ioasic_addrs.h> 20 21#define KN03_SLOT_BASE 0x1f800000 22 23/* 24 * CPU interrupt bits. 25 */ 26#define KN03_CPU_INR_HALT 6 /* HALT button */ 27#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ 28#define KN03_CPU_INR_RES_4 4 /* unused */ 29#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */ 30#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */ 31 32/* 33 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. 34 */ 35#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */ 36#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ 37#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */ 38#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */ 39#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */ 40#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ 41#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ 42#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ 43#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ 44#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ 45#define KN03_IO_INR_RTC 5 /* DS1287 RTC */ 46#define KN03_IO_INR_PSU 4 /* power supply unit warning */ 47#define KN03_IO_INR_RES_3 3 /* unused */ 48#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ 49#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */ 50#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */ 51 52 53/* 54 * Memory Control Register bits. 55 */ 56#define KN03_MCR_RES_16 (0xffff<<16) /* unused */ 57#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ 58#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ 59#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */ 60#define KN03_MCR_RES_11 (0x3<<12) /* unused */ 61#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */ 62#define KN03_MCR_RES_7 (0x7<<7) /* unused */ 63#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */ 64 65/* 66 * I/O ASIC System Support Register bits. 67 */ 68#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ 69#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ 70#define KN03_IO_SSR_RES_12 (1<<12) /* unused */ 71 72#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ 73 74#endif /* __ASM_MIPS_DEC_KN03_H */ 75