1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2/*
3* Copyright 2023 Mobileye Vision Technologies Ltd.
4*/
5
6#include <dt-bindings/interrupt-controller/mips-gic.h>
7
8#include "eyeq5-fixed-clocks.dtsi"
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16		cpu@0 {
17			device_type = "cpu";
18			compatible = "img,i6500";
19			reg = <0>;
20			clocks = <&core0_clk>;
21		};
22	};
23
24	reserved-memory {
25		#address-cells = <2>;
26		#size-cells = <2>;
27		ranges;
28
29		/* These reserved memory regions are also defined in bootmanager
30		* for configuring inbound translation for BARS, don't change
31		* these without syncing with bootmanager
32		*/
33		shmem0_reserved: shmem@804000000 {
34			reg = <0x8 0x04000000 0x0 0x1000000>;
35		};
36		shmem1_reserved: shmem@805000000 {
37			reg = <0x8 0x05000000 0x0 0x1000000>;
38		};
39		pci0_msi_reserved: pci0-msi@806000000 {
40			reg = <0x8 0x06000000 0x0 0x100000>;
41		};
42		pci1_msi_reserved: pci1-msi@806100000 {
43			reg = <0x8 0x06100000 0x0 0x100000>;
44		};
45
46		mini_coredump0_reserved: mini-coredump0@806200000 {
47			reg = <0x8 0x06200000 0x0 0x100000>;
48		};
49		mhm_reserved_0: the-mhm-reserved-0@0 {
50			reg = <0x8 0x00000000 0x0 0x0000800>;
51		};
52	};
53
54	aliases {
55		serial0 = &uart0;
56		serial1 = &uart1;
57		serial2 = &uart2;
58	};
59
60	cpu_intc: interrupt-controller {
61		compatible = "mti,cpu-interrupt-controller";
62		interrupt-controller;
63		#address-cells = <0>;
64		#interrupt-cells = <1>;
65	};
66
67	soc: soc {
68		#address-cells = <2>;
69		#size-cells = <2>;
70		ranges;
71		compatible = "simple-bus";
72
73		uart0: serial@800000 {
74			compatible = "arm,pl011", "arm,primecell";
75			reg = <0 0x800000 0x0 0x1000>;
76			reg-io-width = <4>;
77			interrupt-parent = <&gic>;
78			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
79			clocks  = <&uart_clk>, <&occ_periph>;
80			clock-names = "uartclk", "apb_pclk";
81		};
82
83		uart1: serial@900000 {
84			compatible = "arm,pl011", "arm,primecell";
85			reg = <0 0x900000 0x0 0x1000>;
86			reg-io-width = <4>;
87			interrupt-parent = <&gic>;
88			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
89			clocks  = <&uart_clk>, <&occ_periph>;
90			clock-names = "uartclk", "apb_pclk";
91		};
92
93		uart2: serial@a00000 {
94			compatible = "arm,pl011", "arm,primecell";
95			reg = <0 0xa00000 0x0 0x1000>;
96			reg-io-width = <4>;
97			interrupt-parent = <&gic>;
98			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
99			clocks  = <&uart_clk>, <&occ_periph>;
100			clock-names = "uartclk", "apb_pclk";
101		};
102
103		gic: interrupt-controller@140000 {
104			compatible = "mti,gic";
105			reg = <0x0 0x140000 0x0 0x20000>;
106			interrupt-controller;
107			#interrupt-cells = <3>;
108
109			/*
110			* Declare the interrupt-parent even though the mti,gic
111			* binding doesn't require it, such that the kernel can
112			* figure out that cpu_intc is the root interrupt
113			* controller & should be probed first.
114			*/
115			interrupt-parent = <&cpu_intc>;
116
117			timer {
118				compatible = "mti,gic-timer";
119				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
120				clocks = <&core0_clk>;
121			};
122		};
123	};
124};
125