1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Bit definitions for the MCF54xx ACR and CACR registers. 4 */ 5 6#ifndef m54xxacr_h 7#define m54xxacr_h 8 9/* 10 * Define the Cache register flags. 11 */ 12#define CACR_DEC 0x80000000 /* Enable data cache */ 13#define CACR_DWP 0x40000000 /* Data write protection */ 14#define CACR_DESB 0x20000000 /* Enable data store buffer */ 15#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 16#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 17#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 18#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 19#define CACR_DDCM_P 0x04000000 /* No cache, precise */ 20#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 21#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 22#define CACR_BEC 0x00080000 /* Enable branch cache */ 23#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 24#define CACR_IEC 0x00008000 /* Enable instruction cache */ 25#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 26#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 27#define CACR_IHLCK 0x00000800 /* Instruction cache half lock */ 28#define CACR_IDCM 0x00000400 /* Instruction cache inhibit */ 29#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 30#define CACR_EUSP 0x00000020 /* Enable separate user a7 */ 31 32#define ACR_BASE_POS 24 /* Address Base */ 33#define ACR_MASK_POS 16 /* Address Mask */ 34#define ACR_ENABLE 0x00008000 /* Enable address */ 35#define ACR_USER 0x00000000 /* User mode access only */ 36#define ACR_SUPER 0x00002000 /* Supervisor mode only */ 37#define ACR_ANY 0x00004000 /* Match any access mode */ 38#define ACR_CM_WT 0x00000000 /* Write through mode */ 39#define ACR_CM_CP 0x00000020 /* Copyback mode */ 40#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 41#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 42#define ACR_CM 0x00000060 /* Cache mode mask */ 43#define ACR_SP 0x00000008 /* Supervisor protect */ 44#define ACR_WPROTECT 0x00000004 /* Write protect */ 45 46#define ACR_BA(x) ((x) & 0xff000000) 47#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) 48 49#if defined(CONFIG_M5407) 50 51#define ICACHE_SIZE 0x4000 /* instruction - 16k */ 52#define DCACHE_SIZE 0x2000 /* data - 8k */ 53 54#elif defined(CONFIG_M54xx) 55 56#define ICACHE_SIZE 0x8000 /* instruction - 32k */ 57#define DCACHE_SIZE 0x8000 /* data - 32k */ 58 59#elif defined(CONFIG_M5441x) 60 61#define ICACHE_SIZE 0x2000 /* instruction - 8k */ 62#define DCACHE_SIZE 0x2000 /* data - 8k */ 63#endif 64 65#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 66#define CACHE_WAYS 4 /* 4 ways */ 67 68#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) 69#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) 70#define ICACHE_MAX_ADDR ICACHE_SET_MASK 71#define DCACHE_MAX_ADDR DCACHE_SET_MASK 72 73/* 74 * Version 4 cores have a true harvard style separate instruction 75 * and data cache. Enable data and instruction caches, also enable write 76 * buffers and branch accelerator. 77 */ 78/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ 79/* use '+' instead of '|' for assembler's sake */ 80 81 /* Enable data cache */ 82 /* Enable data store buffer */ 83 /* outside ACRs : No cache, precise */ 84 /* Enable instruction+branch caches */ 85#if defined(CONFIG_M5407) 86#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) 87#else 88#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) 89#endif 90#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 91 92#if defined(CONFIG_MMU) 93/* 94 * If running with the MMU enabled then we need to map the internal 95 * register region as non-cacheable. And then we map all our RAM as 96 * cacheable and supervisor access only. 97 */ 98#define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \ 99 ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) 100#if defined(CONFIG_CACHE_COPYBACK) 101#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 102 ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) 103#else 104#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 105 ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) 106#endif 107#define ACR2_MODE 0 108#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 109 ACR_ENABLE+ACR_SUPER+ACR_SP) 110 111#else 112 113/* 114 * For the non-MMU enabled case we map all of RAM as cacheable. 115 */ 116#if defined(CONFIG_CACHE_COPYBACK) 117#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) 118#else 119#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 120#endif 121#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 122 123#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 124#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) 125#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) 126#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) 127#define ACR1_MODE 0 128#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) 129#define ACR3_MODE 0 130 131#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 132/* Copyback cache mode must push dirty cache lines first */ 133#define CACHE_PUSH 134#endif 135 136#endif /* CONFIG_MMU */ 137#endif /* m54xxacr_h */ 138