1239281Sgonzo// SPDX-License-Identifier: GPL-2.0+
2239281Sgonzo/*
3239281Sgonzo * dts file for Xilinx ZynqMP ZCU1275
4239281Sgonzo *
5239281Sgonzo * (C) Copyright 2017 - 2021, Xilinx, Inc.
6239281Sgonzo *
7239281Sgonzo * Michal Simek <michal.simek@amd.com>
8239281Sgonzo * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
9239281Sgonzo */
10239281Sgonzo
11239281Sgonzo/dts-v1/;
12239281Sgonzo
13239281Sgonzo#include "zynqmp.dtsi"
14239281Sgonzo#include "zynqmp-clk-ccf.dtsi"
15239281Sgonzo
16239281Sgonzo/ {
17239281Sgonzo	model = "ZynqMP ZCU1275 RevA";
18239281Sgonzo	compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
19239281Sgonzo
20239281Sgonzo	aliases {
21239281Sgonzo		serial0 = &uart0;
22239281Sgonzo		serial1 = &dcc;
23239281Sgonzo		spi0 = &qspi;
24239281Sgonzo	};
25239281Sgonzo
26239281Sgonzo	chosen {
27239281Sgonzo		bootargs = "earlycon";
28239281Sgonzo		stdout-path = "serial0:115200n8";
29239281Sgonzo	};
30239281Sgonzo
31239281Sgonzo	memory@0 {
32296980Sloos		device_type = "memory";
33239281Sgonzo		reg = <0x0 0x0 0x0 0x80000000>;
34239281Sgonzo	};
35296980Sloos};
36296980Sloos
37239281Sgonzo&dcc {
38296980Sloos	status = "okay";
39239281Sgonzo};
40296980Sloos
41246276Skientzle&gpio {
42244939Skientzle	status = "okay";
43246276Skientzle};
44244939Skientzle
45244939Skientzle&qspi {
46244939Skientzle	status = "okay";
47244939Skientzle	flash@0 {
48246276Skientzle		compatible = "m25p80", "jedec,spi-nor";
49244939Skientzle		reg = <0x0>;
50246276Skientzle		spi-tx-bus-width = <4>;
51246276Skientzle		spi-rx-bus-width = <4>;
52246276Skientzle		spi-max-frequency = <108000000>;
53246276Skientzle	};
54246276Skientzle};
55246276Skientzle
56246276Skientzle&uart0 {
57246276Skientzle	status = "okay";
58246276Skientzle};
59246276Skientzle