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97fed7ec |
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08-Jan-2024 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Fix comment to be aligned with board name. The board was renamed from zc1275 to zcu1275 but name in comment wasn't updated. Fixes: 370b0e900fb0 ("arm64: zynqmp: Change zc1275 board name to zcu1275") Link: https://lore.kernel.org/r/6e4215807f535d2e2b2b8055aa8574c748fe22e4.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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1d831cad |
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22-May-2023 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> |
arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
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4e4ddd3d |
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29-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Switch to amd.com emails Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
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370b0e90 |
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03-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Change zc1275 board name to zcu1275 Internal board zc1275 was released also to public which ends up with adding missing 'u' to board name. Reflect this change by renaming DT files. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9b50c72c4e634b2c72758eed6275920eedbda06f.1683099606.git.michal.simek@amd.com
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