1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Unisoc UMS9620 DTS file
4 *
5 * Copyright (C) 2023, Unisoc Inc.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	cpus {
16		#address-cells = <2>;
17		#size-cells = <0>;
18
19		cpu-map {
20			cluster0 {
21				core0 {
22					cpu = <&CPU0>;
23				};
24				core1 {
25					cpu = <&CPU1>;
26				};
27				core2 {
28					cpu = <&CPU2>;
29				};
30				core3 {
31					cpu = <&CPU3>;
32				};
33				core4 {
34					cpu = <&CPU4>;
35				};
36				core5 {
37					cpu = <&CPU5>;
38				};
39				core6 {
40					cpu = <&CPU6>;
41				};
42				core7 {
43					cpu = <&CPU7>;
44				};
45			};
46		};
47
48		CPU0: cpu@0 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a55";
51			reg = <0x0 0x0>;
52			enable-method = "psci";
53			cpu-idle-states = <&LIT_CORE_PD>;
54		};
55
56		CPU1: cpu@100 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a55";
59			reg = <0x0 0x100>;
60			enable-method = "psci";
61			cpu-idle-states = <&LIT_CORE_PD>;
62		};
63
64		CPU2: cpu@200 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a55";
67			reg = <0x0 0x200>;
68			enable-method = "psci";
69			cpu-idle-states = <&LIT_CORE_PD>;
70		};
71
72		CPU3: cpu@300 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a55";
75			reg = <0x0 0x300>;
76			enable-method = "psci";
77			cpu-idle-states = <&LIT_CORE_PD>;
78		};
79
80		CPU4: cpu@400 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a76";
83			reg = <0x0 0x400>;
84			enable-method = "psci";
85			cpu-idle-states = <&BIG_CORE_PD>;
86		};
87
88		CPU5: cpu@500 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a76";
91			reg = <0x0 0x500>;
92			enable-method = "psci";
93			cpu-idle-states = <&BIG_CORE_PD>;
94		};
95
96		CPU6: cpu@600 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a76";
99			reg = <0x0 0x600>;
100			enable-method = "psci";
101			cpu-idle-states = <&BIG_CORE_PD>;
102		};
103
104		CPU7: cpu@700 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a76";
107			reg = <0x0 0x700>;
108			enable-method = "psci";
109			cpu-idle-states = <&BIG_CORE_PD>;
110		};
111	};
112
113	idle-states {
114		entry-method = "psci";
115		LIT_CORE_PD: cpu-pd-lit {
116			compatible = "arm,idle-state";
117			entry-latency-us = <1000>;
118			exit-latency-us = <500>;
119			min-residency-us = <2500>;
120			local-timer-stop;
121			arm,psci-suspend-param = <0x00010000>;
122		};
123
124		BIG_CORE_PD: cpu-pd-big {
125			compatible = "arm,idle-state";
126			entry-latency-us = <4000>;
127			exit-latency-us = <4000>;
128			min-residency-us = <10000>;
129			local-timer-stop;
130			arm,psci-suspend-param = <0x00010000>;
131		};
132	};
133
134	psci {
135		compatible = "arm,psci-0.2";
136		method = "smc";
137	};
138
139	timer {
140		compatible = "arm,armv8-timer";
141		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
142			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
143			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
144			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
145	};
146
147	pmu {
148		compatible = "arm,armv8-pmuv3";
149		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
150			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
151			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
152			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
153			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
154			     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
155			     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
156			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
157	};
158
159	soc: soc {
160		compatible = "simple-bus";
161		ranges;
162		#address-cells = <2>;
163		#size-cells = <2>;
164
165		gic: interrupt-controller@12000000 {
166			compatible = "arm,gic-v3";
167			reg = <0x0 0x12000000 0 0x20000>,	/* GICD */
168			      <0x0 0x12040000 0 0x100000>;	/* GICR */
169			#interrupt-cells = <3>;
170			#address-cells = <2>;
171			#size-cells = <2>;
172			redistributor-stride = <0x0 0x20000>;	/* 128KB stride */
173			#redistributor-regions = <1>;
174			interrupt-controller;
175			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
176		};
177
178		apb@20200000 {
179			compatible = "simple-bus";
180			ranges = <0 0 0x20200000 0x100000>;
181			#address-cells = <1>;
182			#size-cells = <1>;
183
184			uart0: serial@0 {
185				compatible = "sprd,ums9620-uart",
186					     "sprd,sc9836-uart";
187				reg = <0 0x100>;
188				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
189				clocks = <&ext_26m>;
190				status = "disabled";
191			};
192
193			uart1: serial@10000 {
194				compatible = "sprd,ums9620-uart",
195					     "sprd,sc9836-uart";
196				reg = <0x10000 0x100>;
197				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
198				clocks = <&ext_26m>;
199				status = "disabled";
200			};
201		};
202	};
203
204	ext_26m: clk-26m {
205		compatible = "fixed-clock";
206		#clock-cells = <0>;
207		clock-frequency = <26000000>;
208		clock-output-names = "ext-26m";
209	};
210
211	ext_4m: clk-4m {
212		compatible = "fixed-clock";
213		#clock-cells = <0>;
214		clock-frequency = <4000000>;
215		clock-output-names = "ext-4m";
216	};
217
218	ext_32k: clk-32k {
219		compatible = "fixed-clock";
220		#clock-cells = <0>;
221		clock-frequency = <32768>;
222		clock-output-names = "ext-32k";
223	};
224
225	rco_100m: clk-100m {
226		compatible = "fixed-clock";
227		#clock-cells = <0>;
228		clock-frequency = <100000000>;
229		clock-output-names = "rco-100m";
230	};
231
232	dphy_312m5: dphy-312m5 {
233		compatible = "fixed-clock";
234		#clock-cells = <0>;
235		clock-frequency = <312500000>;
236		clock-output-names = "dphy-312m5";
237	};
238
239	dphy_416m7: dphy-416m7 {
240		compatible = "fixed-clock";
241		#clock-cells = <0>;
242		clock-frequency = <416700000>;
243		clock-output-names = "dphy-416m7";
244	};
245};
246