1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017-2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mq.dtsi"
9#include <dt-bindings/interrupt-controller/irq.h>
10
11/ {
12	model = "Google i.MX8MQ Phanbell";
13	compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0x40000000>;
22	};
23
24	pmic_osc: clock-pmic {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <32768>;
28		clock-output-names = "pmic_osc";
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
32		compatible = "regulator-fixed";
33		regulator-name = "VSD_3V3";
34		regulator-min-microvolt = <3300000>;
35		regulator-max-microvolt = <3300000>;
36		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
37		enable-active-high;
38	};
39
40	fan: gpio-fan {
41		compatible = "gpio-fan";
42		gpio-fan,speed-map = <0 0>, <8600 1>;
43		gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
44		#cooling-cells = <2>;
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_gpio_fan>;
47		status = "okay";
48	};
49};
50
51&A53_0 {
52	cpu-supply = <&buck2>;
53};
54
55&A53_1 {
56	cpu-supply = <&buck2>;
57};
58
59&A53_2 {
60	cpu-supply = <&buck2>;
61};
62
63&A53_3 {
64	cpu-supply = <&buck2>;
65};
66
67&cpu_thermal {
68	trips {
69		cpu_alert0: trip0 {
70			temperature = <75000>;
71			hysteresis = <2000>;
72			type = "passive";
73		};
74
75		cpu_alert1: trip1 {
76			temperature = <80000>;
77			hysteresis = <2000>;
78			type = "passive";
79		};
80
81		cpu_crit0: trip3 {
82			temperature = <90000>;
83			hysteresis = <2000>;
84			type = "critical";
85		};
86
87		fan_toggle0: trip4 {
88			temperature = <65000>;
89			hysteresis = <10000>;
90			type = "active";
91		};
92	};
93
94	cooling-maps {
95		map0 {
96			trip = <&cpu_alert0>;
97			cooling-device =
98			<&A53_0 0 1>; /* Exclude highest OPP */
99		};
100
101		map1 {
102			trip = <&cpu_alert1>;
103			cooling-device =
104			<&A53_0 0 2>; /* Exclude two highest OPPs */
105		};
106
107		map4 {
108			trip = <&fan_toggle0>;
109			cooling-device = <&fan 0 1>;
110		};
111	};
112};
113
114&i2c1 {
115	clock-frequency = <400000>;
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_i2c1>;
118	status = "okay";
119
120	pmic: pmic@4b {
121		compatible = "rohm,bd71837";
122		reg = <0x4b>;
123		pinctrl-names = "default";
124		pinctrl-0 = <&pinctrl_pmic>;
125		#clock-cells = <0>;
126		clocks = <&pmic_osc>;
127		clock-output-names = "pmic_clk";
128		interrupt-parent = <&gpio1>;
129		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
130
131		regulators {
132			buck1: BUCK1 {
133				regulator-name = "buck1";
134				regulator-min-microvolt = <700000>;
135				regulator-max-microvolt = <1300000>;
136				regulator-boot-on;
137				regulator-always-on;
138				regulator-ramp-delay = <1250>;
139				rohm,dvs-run-voltage = <900000>;
140				rohm,dvs-idle-voltage = <900000>;
141				rohm,dvs-suspend-voltage = <800000>;
142			};
143
144			buck2: BUCK2 {
145				regulator-name = "buck2";
146				regulator-min-microvolt = <850000>;
147				regulator-max-microvolt = <1000000>;
148				regulator-boot-on;
149				regulator-always-on;
150				rohm,dvs-run-voltage = <1000000>;
151				rohm,dvs-idle-voltage = <900000>;
152			};
153
154			buck3: BUCK3 {
155				regulator-name = "buck3";
156				regulator-min-microvolt = <700000>;
157				regulator-max-microvolt = <1300000>;
158				regulator-boot-on;
159				rohm,dvs-run-voltage = <900000>;
160			};
161
162			buck4: BUCK4 {
163				regulator-name = "buck4";
164				regulator-min-microvolt = <700000>;
165				regulator-max-microvolt = <1300000>;
166				regulator-boot-on;
167				regulator-always-on;
168				rohm,dvs-run-voltage = <900000>;
169			};
170
171			buck5: BUCK5 {
172				regulator-name = "buck5";
173				regulator-min-microvolt = <700000>;
174				regulator-max-microvolt = <1350000>;
175				regulator-boot-on;
176				regulator-always-on;
177			};
178
179			buck6: BUCK6 {
180				regulator-name = "buck6";
181				regulator-min-microvolt = <3000000>;
182				regulator-max-microvolt = <3300000>;
183				regulator-boot-on;
184				regulator-always-on;
185			};
186
187			buck7: BUCK7 {
188				regulator-name = "buck7";
189				regulator-min-microvolt = <1605000>;
190				regulator-max-microvolt = <1995000>;
191				regulator-boot-on;
192				regulator-always-on;
193			};
194
195			buck8: BUCK8 {
196				regulator-name = "buck8";
197				regulator-min-microvolt = <800000>;
198				regulator-max-microvolt = <1400000>;
199				regulator-boot-on;
200				regulator-always-on;
201			};
202
203			ldo1: LDO1 {
204				regulator-name = "ldo1";
205				regulator-min-microvolt = <3000000>;
206				regulator-max-microvolt = <3300000>;
207				regulator-boot-on;
208				regulator-always-on;
209			};
210
211			ldo2: LDO2 {
212				regulator-name = "ldo2";
213				regulator-min-microvolt = <900000>;
214				regulator-max-microvolt = <900000>;
215				regulator-boot-on;
216				regulator-always-on;
217			};
218
219			ldo3: LDO3 {
220				regulator-name = "ldo3";
221				regulator-min-microvolt = <1800000>;
222				regulator-max-microvolt = <3300000>;
223				regulator-boot-on;
224				regulator-always-on;
225			};
226
227			ldo4: LDO4 {
228				regulator-name = "ldo4";
229				regulator-min-microvolt = <900000>;
230				regulator-max-microvolt = <1800000>;
231				regulator-boot-on;
232				regulator-always-on;
233			};
234
235			ldo5: LDO5 {
236				regulator-name = "ldo5";
237				regulator-min-microvolt = <1800000>;
238				regulator-max-microvolt = <3300000>;
239				regulator-boot-on;
240				regulator-always-on;
241			};
242
243			ldo6: LDO6 {
244				regulator-name = "ldo6";
245				regulator-min-microvolt = <900000>;
246				regulator-max-microvolt = <1800000>;
247				regulator-boot-on;
248				regulator-always-on;
249			};
250
251			ldo7: LDO7 {
252				regulator-name = "ldo7";
253				regulator-min-microvolt = <1800000>;
254				regulator-max-microvolt = <3300000>;
255				regulator-boot-on;
256				regulator-always-on;
257			};
258		};
259	};
260};
261
262&fec1 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&pinctrl_fec1>;
265	phy-mode = "rgmii-id";
266	phy-handle = <&ethphy0>;
267	fsl,magic-packet;
268	status = "okay";
269
270	mdio {
271		#address-cells = <1>;
272		#size-cells = <0>;
273		ethphy0: ethernet-phy@0 {
274			compatible = "ethernet-phy-ieee802.3-c22";
275			reg = <0>;
276			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
277			reset-assert-us = <10000>;
278			reset-deassert-us = <50000>;
279		};
280	};
281};
282
283&uart1 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_uart1>;
286	status = "okay";
287};
288
289&usdhc1 {
290	pinctrl-names = "default", "state_100mhz", "state_200mhz";
291	pinctrl-0 = <&pinctrl_usdhc1>;
292	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
293	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
294	bus-width = <8>;
295	non-removable;
296	status = "okay";
297};
298
299&usdhc2 {
300	pinctrl-names = "default", "state_100mhz", "state_200mhz";
301	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
302	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
303	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304	bus-width = <4>;
305	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
306	vmmc-supply = <&reg_usdhc2_vmmc>;
307	status = "okay";
308};
309
310&usb3_phy0 {
311	status = "okay";
312};
313
314&usb_dwc3_0 {
315	dr_mode = "otg";
316	status = "okay";
317};
318
319&usb3_phy1 {
320	status = "okay";
321};
322
323&usb_dwc3_1 {
324	dr_mode = "host";
325	status = "okay";
326};
327
328&wdog1 {
329	pinctrl-names = "default";
330	pinctrl-0 = <&pinctrl_wdog>;
331	fsl,ext-reset-output;
332	status = "okay";
333};
334
335&iomuxc {
336	pinctrl_fec1: fec1grp {
337		fsl,pins = <
338			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
339			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
340			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
341			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
342			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
343			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
344			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
345			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
346			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
347			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
348			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
349			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
350			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
351			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
352			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
353		>;
354	};
355
356	pinctrl_gpio_fan: gpiofangrp {
357		fsl,pins = <
358			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x16
359		>;
360	};
361
362	pinctrl_i2c1: i2c1grp {
363		fsl,pins = <
364			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
365			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
366		>;
367	};
368
369	pinctrl_pmic: pmicirqgrp {
370		fsl,pins = <
371			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
372		>;
373	};
374
375	pinctrl_uart1: uart1grp {
376		fsl,pins = <
377			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
378			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
379		>;
380	};
381
382	pinctrl_usdhc1: usdhc1grp {
383		fsl,pins = <
384			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
385			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
386			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
387			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
388			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
389			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
390			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
391			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
392			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
393			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
394			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
395			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
396		>;
397	};
398
399	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
400		fsl,pins = <
401			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
402			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
403			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
404			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
405			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
406			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
407			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
408			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
409			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
410			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
411			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
412			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
413		>;
414	};
415
416	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
417		fsl,pins = <
418			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
419			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
420			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
421			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
422			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
423			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
424			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
425			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
426			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
427			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
428			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
429			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
430		>;
431	};
432
433	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
434		fsl,pins = <
435			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
436			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
437		>;
438	};
439
440	pinctrl_usdhc2: usdhc2grp {
441		fsl,pins = <
442			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
443			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
444			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
445			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
446			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
447			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
448			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
449		>;
450	};
451
452	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
453		fsl,pins = <
454			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
455			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
456			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
457			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
458			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
459			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
460			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
461		>;
462	};
463
464	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
465		fsl,pins = <
466			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
467			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
468			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
469			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
470			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
471			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
472			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
473		>;
474	};
475
476	pinctrl_wdog: wdoggrp {
477		fsl,pins = <
478			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
479		>;
480	};
481};
482