1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/reset/amlogic,c3-reset.h>
10
11/ {
12	cpus {
13		#address-cells = <2>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "arm,cortex-a35";
19			reg = <0x0 0x0>;
20			enable-method = "psci";
21		};
22
23		cpu1: cpu@1 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a35";
26			reg = <0x0 0x1>;
27			enable-method = "psci";
28		};
29	};
30
31	timer {
32		compatible = "arm,armv8-timer";
33		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
34			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
35			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
36			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
37	};
38
39	psci {
40		compatible = "arm,psci-1.0";
41		method = "smc";
42	};
43
44	xtal: xtal-clk {
45		compatible = "fixed-clock";
46		clock-frequency = <24000000>;
47		clock-output-names = "xtal";
48		#clock-cells = <0>;
49	};
50
51	sm: secure-monitor {
52		compatible = "amlogic,meson-gxbb-sm";
53
54		pwrc: power-controller {
55			compatible = "amlogic,c3-pwrc";
56			#power-domain-cells = <1>;
57		};
58	};
59
60	soc {
61		compatible = "simple-bus";
62		#address-cells = <2>;
63		#size-cells = <2>;
64		ranges;
65
66		gic: interrupt-controller@fff01000 {
67			compatible = "arm,gic-400";
68			#interrupt-cells = <3>;
69			#address-cells = <0>;
70			interrupt-controller;
71			reg = <0x0 0xfff01000 0 0x1000>,
72			      <0x0 0xfff02000 0 0x2000>,
73			      <0x0 0xfff04000 0 0x2000>,
74			      <0x0 0xfff06000 0 0x2000>;
75			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
76		};
77
78		apb4: bus@fe000000 {
79			compatible = "simple-bus";
80			reg = <0x0 0xfe000000 0x0 0x480000>;
81			#address-cells = <2>;
82			#size-cells = <2>;
83			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
84
85			reset: reset-controller@2000 {
86				compatible = "amlogic,c3-reset";
87				reg = <0x0 0x2000 0x0 0x98>;
88				#reset-cells = <1>;
89			};
90
91			watchdog@2100 {
92				compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
93				reg = <0x0 0x2100 0x0 0x10>;
94				clocks = <&xtal>;
95			};
96
97			periphs_pinctrl: pinctrl@4000 {
98				compatible = "amlogic,c3-periphs-pinctrl";
99				#address-cells = <2>;
100				#size-cells = <2>;
101				ranges;
102
103				gpio: bank@4000 {
104					reg = <0x0 0x4000 0x0 0x004c>,
105					      <0x0 0x4100 0x0 0x01de>;
106					reg-names = "mux", "gpio";
107					gpio-controller;
108					#gpio-cells = <2>;
109					gpio-ranges = <&periphs_pinctrl 0 0 55>;
110				};
111			};
112
113			gpio_intc: interrupt-controller@4080 {
114				compatible = "amlogic,meson-gpio-intc",
115					     "amlogic,c3-gpio-intc";
116				reg = <0x0 0x4080 0x0 0x0020>;
117				interrupt-controller;
118				#interrupt-cells = <2>;
119				amlogic,channel-interrupts =
120					<10 11 12 13 14 15 16 17 18 19 20 21>;
121			};
122
123			uart_b: serial@7a000 {
124				compatible = "amlogic,meson-s4-uart",
125					   "amlogic,meson-ao-uart";
126				reg = <0x0 0x7a000 0x0 0x18>;
127				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
128				status = "disabled";
129				clocks = <&xtal>, <&xtal>, <&xtal>;
130				clock-names = "xtal", "pclk", "baud";
131			};
132
133		};
134	};
135};
136