1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS file for AMD Seattle SoC
4 *
5 * Copyright (C) 2014 Advanced Micro Devices, Inc.
6 */
7
8/ {
9	compatible = "amd,seattle";
10	interrupt-parent = <&gic0>;
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	gic0: interrupt-controller@e1101000 {
15		compatible = "arm,gic-400", "arm,cortex-a15-gic";
16		interrupt-controller;
17		#interrupt-cells = <3>;
18		#address-cells = <2>;
19		#size-cells = <2>;
20		reg = <0x0 0xe1110000 0 0x1000>,
21		      <0x0 0xe112f000 0 0x2000>,
22		      <0x0 0xe1140000 0 0x2000>,
23		      <0x0 0xe1160000 0 0x2000>;
24		interrupts = <1 9 0xf04>;
25		ranges = <0 0 0 0xe1100000 0 0x100000>;
26		v2m0: v2m@e0080000 {
27			compatible = "arm,gic-v2m-frame";
28			msi-controller;
29			reg = <0x0 0x00080000 0 0x1000>;
30		};
31	};
32
33	timer {
34		compatible = "arm,armv8-timer";
35		interrupts = <1 13 0xff04>,
36			     <1 14 0xff04>,
37			     <1 11 0xff04>,
38			     <1 10 0xff04>;
39	};
40
41	smb0: smb {
42		compatible = "simple-bus";
43		#address-cells = <2>;
44		#size-cells = <2>;
45		ranges;
46
47		/*
48		 * dma-ranges is 40-bit address space containing:
49		 * - GICv2m MSI register is at 0xe0080000
50		 * - DRAM range [0x8000000000 to 0xffffffffff]
51		 */
52		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
53
54		/include/ "amd-seattle-clks.dtsi"
55
56		sata0: sata@e0300000 {
57			compatible = "snps,dwc-ahci";
58			reg = <0 0xe0300000 0 0xf0000>;
59			interrupts = <0 355 4>;
60			clocks = <&sataclk_333mhz>;
61			iommus = <&sata0_smmu 0x0 0x1f>;
62			dma-coherent;
63		};
64
65		/* This is for Rev B only */
66		sata1: sata@e0d00000 {
67			status = "disabled";
68			compatible = "snps,dwc-ahci";
69			reg = <0 0xe0d00000 0 0xf0000>;
70			interrupts = <0 354 4>;
71			clocks = <&sataclk_333mhz>;
72			iommus = <&sata1_smmu 0x0e>,
73				 <&sata1_smmu 0x0f>,
74				 <&sata1_smmu 0x1e>;
75			dma-coherent;
76		};
77
78		sata0_smmu: iommu@e0200000 {
79			compatible = "arm,mmu-401";
80			reg = <0 0xe0200000 0 0x10000>;
81			#global-interrupts = <1>;
82			interrupts = <0 332 4>, <0 332 4>;
83			#iommu-cells = <2>;
84			dma-coherent;
85		};
86
87		sata1_smmu: iommu@e0c00000 {
88			compatible = "arm,mmu-401";
89			reg = <0 0xe0c00000 0 0x10000>;
90			#global-interrupts = <1>;
91			interrupts = <0 331 4>, <0 331 4>;
92			#iommu-cells = <1>;
93			dma-coherent;
94		};
95
96		i2c0: i2c@e1000000 {
97			status = "disabled";
98			compatible = "snps,designware-i2c";
99			reg = <0 0xe1000000 0 0x1000>;
100			interrupts = <0 357 4>;
101			clocks = <&miscclk_250mhz>;
102		};
103
104		i2c1: i2c@e0050000 {
105			status = "disabled";
106			compatible = "snps,designware-i2c";
107			reg = <0 0xe0050000 0 0x1000>;
108			interrupts = <0 340 4>;
109			clocks = <&miscclk_250mhz>;
110		};
111
112		serial0: serial@e1010000 {
113			compatible = "arm,pl011", "arm,primecell";
114			reg = <0 0xe1010000 0 0x1000>;
115			interrupts = <0 328 4>;
116			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
117			clock-names = "uartclk", "apb_pclk";
118		};
119
120		spi0: spi@e1020000 {
121			status = "disabled";
122			compatible = "arm,pl022", "arm,primecell";
123			reg = <0 0xe1020000 0 0x1000>;
124			spi-controller;
125			interrupts = <0 330 4>;
126			clocks = <&uartspiclk_100mhz>;
127			clock-names = "apb_pclk";
128		};
129
130		spi1: spi@e1030000 {
131			status = "disabled";
132			compatible = "arm,pl022", "arm,primecell";
133			reg = <0 0xe1030000 0 0x1000>;
134			spi-controller;
135			interrupts = <0 329 4>;
136			clocks = <&uartspiclk_100mhz>;
137			clock-names = "apb_pclk";
138			num-cs = <1>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141		};
142
143		gpio0: gpio@e1040000 { /* Not available to OS for B0 */
144			status = "disabled";
145			compatible = "arm,pl061", "arm,primecell";
146			#gpio-cells = <2>;
147			reg = <0 0xe1040000 0 0x1000>;
148			gpio-controller;
149			interrupts = <0 359 4>;
150			interrupt-controller;
151			#interrupt-cells = <2>;
152			clocks = <&miscclk_250mhz>;
153			clock-names = "apb_pclk";
154		};
155
156		gpio1: gpio@e1050000 { /* [0:7] */
157			status = "disabled";
158			compatible = "arm,pl061", "arm,primecell";
159			#gpio-cells = <2>;
160			reg = <0 0xe1050000 0 0x1000>;
161			gpio-controller;
162			interrupt-controller;
163			#interrupt-cells = <2>;
164			interrupts = <0 358 4>;
165			clocks = <&miscclk_250mhz>;
166			clock-names = "apb_pclk";
167		};
168
169		gpio2: gpio@e0020000 { /* [8:15] */
170			status = "disabled";
171			compatible = "arm,pl061", "arm,primecell";
172			#gpio-cells = <2>;
173			reg = <0 0xe0020000 0 0x1000>;
174			gpio-controller;
175			interrupt-controller;
176			#interrupt-cells = <2>;
177			interrupts = <0 366 4>;
178			clocks = <&miscclk_250mhz>;
179			clock-names = "apb_pclk";
180		};
181
182		gpio3: gpio@e0030000 { /* [16:23] */
183			status = "disabled";
184			compatible = "arm,pl061", "arm,primecell";
185			#gpio-cells = <2>;
186			reg = <0 0xe0030000 0 0x1000>;
187			gpio-controller;
188			interrupt-controller;
189			#interrupt-cells = <2>;
190			interrupts = <0 365 4>;
191			clocks = <&miscclk_250mhz>;
192			clock-names = "apb_pclk";
193		};
194
195		gpio4: gpio@e0080000 { /* [24] */
196			status = "disabled";
197			compatible = "arm,pl061", "arm,primecell";
198			#gpio-cells = <2>;
199			reg = <0 0xe0080000 0 0x1000>;
200			gpio-controller;
201			interrupt-controller;
202			#interrupt-cells = <2>;
203			interrupts = <0 361 4>;
204			clocks = <&miscclk_250mhz>;
205			clock-names = "apb_pclk";
206		};
207
208		ccp0: ccp@e0100000 {
209			status = "disabled";
210			compatible = "amd,ccp-seattle-v1a";
211			reg = <0 0xe0100000 0 0x10000>;
212			interrupts = <0 3 4>;
213			dma-coherent;
214			iommus = <&sata1_smmu 0x00>,
215				 <&sata1_smmu 0x02>,
216				 <&sata1_smmu 0x40>,
217				 <&sata1_smmu 0x42>;
218		};
219
220		pcie0: pcie@f0000000 {
221			compatible = "pci-host-ecam-generic";
222			#address-cells = <3>;
223			#size-cells = <2>;
224			#interrupt-cells = <1>;
225			device_type = "pci";
226			bus-range = <0 0x7f>;
227			msi-parent = <&v2m0>;
228			reg = <0 0xf0000000 0 0x10000000>;
229
230			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
231			interrupt-map =
232				<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
233				<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
234				<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
235				<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
236
237				<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
238				<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
239				<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
240				<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
241
242				<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
243				<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
244				<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
245				<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
246
247			dma-coherent;
248			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
249			ranges =
250				/* I/O Memory (size=64K) */
251				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
252				/* 32-bit MMIO (size=2G) */
253				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
254				/* 64-bit MMIO (size= 508G) */
255				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
256			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
257		};
258
259		pcie_smmu: iommu@e0a00000 {
260			compatible = "arm,mmu-401";
261			reg = <0 0xe0a00000 0 0x10000>;
262			#global-interrupts = <1>;
263			interrupts = <0 333 4>, <0 333 4>;
264			#iommu-cells = <1>;
265			dma-coherent;
266		};
267
268		/* Perf CCN504 PMU */
269		ccn: ccn@e8000000 {
270			compatible = "arm,ccn-504";
271			reg = <0x0 0xe8000000 0 0x1000000>;
272			interrupts = <0 380 4>;
273		};
274
275		ipmi_kcs: kcs@e0010000 {
276			status = "disabled";
277			compatible = "ipmi-kcs";
278			device_type = "ipmi";
279			reg = <0x0 0xe0010000 0 0x8>;
280			interrupts = <0 389 4>;
281			reg-size = <1>;
282			reg-spacing = <4>;
283		};
284	};
285};
286