1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Tony Xie <tony.xie@rock-chips.com>
5 */
6
7#ifndef __MACH_ROCKCHIP_PM_H
8#define __MACH_ROCKCHIP_PM_H
9
10extern unsigned long rkpm_bootdata_cpusp;
11extern unsigned long rkpm_bootdata_cpu_code;
12extern unsigned long rkpm_bootdata_l2ctlr_f;
13extern unsigned long rkpm_bootdata_l2ctlr;
14extern unsigned long rkpm_bootdata_ddr_code;
15extern unsigned long rkpm_bootdata_ddr_data;
16extern unsigned long rk3288_bootram_sz;
17
18void rockchip_slp_cpu_resume(void);
19#ifdef CONFIG_PM_SLEEP
20void __init rockchip_suspend_init(void);
21#else
22static inline void rockchip_suspend_init(void)
23{
24}
25#endif
26
27/****** following is rk3288 defined **********/
28#define RK3288_PMU_WAKEUP_CFG0		0x00
29#define RK3288_PMU_WAKEUP_CFG1		0x04
30#define RK3288_PMU_PWRMODE_CON		0x18
31#define RK3288_PMU_OSC_CNT		0x20
32#define RK3288_PMU_PLL_CNT		0x24
33#define RK3288_PMU_STABL_CNT		0x28
34#define RK3288_PMU_DDR0IO_PWRON_CNT	0x2c
35#define RK3288_PMU_DDR1IO_PWRON_CNT	0x30
36#define RK3288_PMU_CORE_PWRDWN_CNT	0x34
37#define RK3288_PMU_CORE_PWRUP_CNT	0x38
38#define RK3288_PMU_GPU_PWRDWN_CNT	0x3c
39#define RK3288_PMU_GPU_PWRUP_CNT	0x40
40#define RK3288_PMU_WAKEUP_RST_CLR_CNT	0x44
41#define RK3288_PMU_PWRMODE_CON1		0x90
42
43#define RK3288_SGRF_SOC_CON0		(0x0000)
44#define RK3288_SGRF_FAST_BOOT_ADDR	(0x0120)
45#define SGRF_PCLK_WDT_GATE		BIT(6)
46#define SGRF_PCLK_WDT_GATE_WRITE	BIT(22)
47#define SGRF_FAST_BOOT_EN		BIT(8)
48#define SGRF_FAST_BOOT_EN_WRITE		BIT(24)
49
50#define RK3288_SGRF_CPU_CON0		(0x40)
51#define SGRF_DAPDEVICEEN		BIT(0)
52#define SGRF_DAPDEVICEEN_WRITE		BIT(16)
53
54/* PMU_WAKEUP_CFG1 bits */
55#define PMU_ARMINT_WAKEUP_EN		BIT(0)
56#define PMU_GPIOINT_WAKEUP_EN		BIT(3)
57
58enum rk3288_pwr_mode_con {
59	PMU_PWR_MODE_EN = 0,
60	PMU_CLK_CORE_SRC_GATE_EN,
61	PMU_GLOBAL_INT_DISABLE,
62	PMU_L2FLUSH_EN,
63	PMU_BUS_PD_EN,
64	PMU_A12_0_PD_EN,
65	PMU_SCU_EN,
66	PMU_PLL_PD_EN,
67	PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
68	PMU_PWROFF_COMB,
69	PMU_ALIVE_USE_LF,
70	PMU_PMU_USE_LF,
71	PMU_OSC_24M_DIS,
72	PMU_INPUT_CLAMP_EN,
73	PMU_WAKEUP_RESET_EN,
74	PMU_SREF0_ENTER_EN,
75	PMU_SREF1_ENTER_EN,
76	PMU_DDR0IO_RET_EN,
77	PMU_DDR1IO_RET_EN,
78	PMU_DDR0_GATING_EN,
79	PMU_DDR1_GATING_EN,
80	PMU_DDR0IO_RET_DE_REQ,
81	PMU_DDR1IO_RET_DE_REQ
82};
83
84enum rk3288_pwr_mode_con1 {
85	PMU_CLR_BUS = 0,
86	PMU_CLR_CORE,
87	PMU_CLR_CPUP,
88	PMU_CLR_ALIVE,
89	PMU_CLR_DMA,
90	PMU_CLR_PERI,
91	PMU_CLR_GPU,
92	PMU_CLR_VIDEO,
93	PMU_CLR_HEVC,
94	PMU_CLR_VIO,
95};
96
97#endif /* __MACH_ROCKCHIP_PM_H */
98